Industry-university Cooperation Foundation Hanyang University

Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

University of Seoul Industry Cooperation Foundation

Skhynix Inc.

Hynix Semiconductor Inc.

Chang Sik Yoo

Young Jin Moon

Yong Seong Roh

Sang Wook Kwon

Ki Young Kim

Dong Zo Kim

Joong Ho Choi

Nam Yun Kim

Yun Kwon Park

Jin Sung Choi

Yu Jin Jang

Jeong Mo Yang

Young Ho Ryu

Chang Wook Yoon

Keum Su Song

Chun Seok Jeong

Hwan Chul Cho

Jang Woo Lee

Jeong Pyo Park

Jae Jin Lee

Chi Hyung Ahn

Jae Shin Lee

Seok Joon Kang

Jae Hyun Park

Eun Seok Park

Young Tack Hong

Jung Chul Gong

Kye-hyun Kyung

Bong Chul Kim

Byoung Hee Lee

Kee Teok Park

Seong Joong Kim

Jung Sun Kwon

Joon Youp Sung

Jin Kwan Park

Hyeong Min Seo

Ji Yun Han

Ho Joon Jang

Hyun Ah An

Baek Jin Lim

Yung Jin Moon

Sung Woo Yoon

Hong Jung Kim

A low power PAM-4 output transmitter is disclosed. The lower power PAM-4 output transmitter comprises a first source series terminated SST branch configured to include unit cells having transistors which are selectively activated in response to an input signal outputted from an encoder; a second SST branch configured to include unit cells having transistors which are selectively activated in response to a negative signal of the input signal; and a common voltage switch H3 configured to short or open the first SST branch and the second SST branch. Here, differential signals are outputted from both terminals of the first SST branch and the second SST branch by making the first SST branch and the second SST branch short or open according to an operation of the common voltage switch.

Low power PAM-4 output transmitter

A multiplexer includes a first inverter for receiving and inverting first data, a second inverter for receiving and inverting second data, and a first driver connected to an output of the first inverter and to an output of the second inverter. The first driver is configured to output the first data or the second data as output data.

Multiplexer

Disclosed are high-speed data transmitting/receiving system and method capable of removing simultaneous switching noise and ISI at low cost and a small area. A transmitter used in the data transmitting/receiving system includes: a data mapping unit which maps 2-bit input data to one of codes, wherein the voltage level of a first signal line, the voltage level of a second signal line, and the voltage level of a third signal line are set in each of the codes; and a transmit driver which outputs data corresponding to the input data through the first signal line, the second signal line, and the third signal line having the voltage levels corresponding to the mapped code. Here, each of the voltage levels is '+1', '0' or &#x2018;&#x2212;1&#x2019;, and the number of signal lines having the voltage level of &#x2018;+1&#x2019; is the same as the number of signal lines having the voltage level of &#x2018;&#x2212;1&#x2019;.

High-speed data transmitting/receiving system and method of removing simultaneous switching noise and inter-symbol interference

Disclosed are a transmitter capable of cancelling simultaneous switching noise while ensuring low costs and a small area and a data transmission method in the same. The transmitter includes an encoder configured to convert input data of two levels (1 and 0) into data of three levels (+1, 0, and &#x2212;1) and an output unit configured to output the data converted by the encoder. Here, the encoder adds 1 bit to the input data such that the number of bits corresponding to logic 1 becomes an even number. In addition, a specific correlation is established between currents or voltages corresponding to at least two levels of levels '+1', '0', and &#x201c;&#x2212;1&#x201d; so that &#x201c;+1&#x201d; and &#x201c;&#x2212;1&#x201d; corresponding to the logic 1 are alternately arranged and a current flowing through a power line or a ground line is constant regardless of the input data.

Transmitter for cancelling simultaneous switching noise and data transmission method in the same

The signal transmission device converts a K-bit original signal into an N-bit (N is greater than K) transmission signal in which the number of a logic high bit is identical to the number of a logic low bit, according to a lookup table in which a plurality of K-bit original signals are associated with a plurality of N-bit transmission signals by 1:1 correspondence, and transmit the N-bit transmission signal via N signal lines such that each line carries one bit, thereby minimizing the noise affecting the K-bit original signal.

Signal transmission device and method, and signal reception device

A digital phase locked loop realizing high bandwidth is disclosed. The digital locked loop generates a first digital code corresponding to a difference between a rising edge of a reference signal and a rising edge of a feedback signal and a second digital code corresponding to a difference between a falling edge of the reference signal and a falling edges of the feedback signal, generates a third digital code by adding the first digital code and the second digital code, generates a first frequency control code at the rising edge of the reference signal and a second frequency control code at the falling edge of the reference signal by filtering the third digital code, outputs a specific frequency depending on the first frequency control code and the second frequency control code.

Digital phase locked loop

Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage control oscillator by comparing both a phase difference between rising edge of a reference signal and rising edge of a feedback signal and a phase difference between falling edge of the reference signal and falling edge of the feedback signal.

Phase-locked loop with high bandwidth using rising edge and falling edge of signal

An apparatus and a method for charge control are provided. The apparatus for charge control may include an integrated direct current-to-direct current (DC/DC) converter configured to step up an output voltage level of a load to be greater than or equal to a supply voltage level set in a power amplifier, and the power amplifier configured to convert a direct current (DC) voltage stepped up by the integrated DC/DC converter into an alternating current (AC) voltage based on a resonant frequency, and to amplify the converted AC voltage. The apparatus for charge control may include a rectification unit configured to convert an AC power received wirelessly into a DC power; and a DC/DC converter configured to step down a voltage level of the DC power to a voltage level required by a load in the receiving mode.

Apparatus and method for charging control in wireless charging system

Apparatus and method for charge control in wireless charging system

A method of compensating for reverse current leakage in an active rectifier may include advancing an output of a comparator by a predetermined period of time by applying a predetermined offset voltage to a reference voltage input to the comparator, and activating a switch based on the output of the comparator. The method may also include deactivating the switch when a predetermined time delay elapses from a point in time at which the switch was activated.

Active rectifier and circuit for compensating for reverse current leakage using time delay scheme for zero reverse leakage current

An apparatus and a method for wireless power reception are provided. A wireless power receiver includes a receiving unit configured to wirelessly receive a power. The wireless power receiver further includes a power consuming unit configured to consume the power, until a voltage applied to a load reaches a predetermined value, so that an amount of a power transferred from the receiving unit to the load is less than or equal to an initial accommodation power amount of the load.

Apparatus and method for wireless power reception

An active rectifier and a wireless power receiver including the active rectifier are provided. According to an aspect, an active rectifier may include: a first loop configured to provide voltage when the phase of an input signal is positive; and a second loop configured to provide voltage when the phase of the input signal is negative, wherein the first loop and the second loop include a delay locked loop configured to compensate for reverse current leakage due to a delay of a switch included therein.

Active rectifier with delay locked loop to compensate for reverse current leakage and wireless power receiving apparatus including active rectifier with delay locked loop to compensate for reverse current leakage

There are provided a phase shift circuit and a power factor correction circuit including the same. The phase shift circuit includes a switching circuit unit charging power in or discharging power from a capacitor through a plurality of switching devices and comparing a voltage of the capacitor with a predetermined reference voltage, and a clock generating unit generating a reference clock signal based on an output of the switching circuit unit, wherein the switching circuit unit turns the plurality of switching devices on or off, based on currents from inductors respectively included in a main circuit and a sub-circuit of a power factor correction circuit to determine a polarity of the voltage of the capacitor.

Phase shift circuit and power factor correction circuit including the same

A phase shift circuit may include a ramp generation unit charging or discharging a capacitor connected to a switch device to generate a ramp signal, a reference signal generation unit generating a predetermined reference signal from the ramp signal, and a comparison unit comparing the ramp signal with the reference signal to generate a clock signal, wherein at least one of the reference signal generation unit and the comparison unit changes a negative or positive value of offset components included in the reference signal or the ramp signal within every operating period of the switch device.

There is provided a power factor correction circuit including: a power conversion circuit unit controlling an inductor current according to a switching signal applied to a main switch to convert an external input voltage into an output voltage having a predetermined range; an imbalance detection circuit outputting an imbalance state signal when the external input voltage is in an unbalanced state by using the inductor current; and a soft start circuit unit performing soft starting by adjusting the switching signal when the imbalance state signal is output by the imbalance detection circuit unit.

Power factor correction circuit

Growing community of inventors

Seoul, South Korea

Chang Sik Yoo