Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Skhynix Inc.

Hynix Semiconductor Inc.

Other

Core Logic Inc.

Chang-Sik Yoo

Kye-hyun Kyung

Kee-hoon Lee

Chun-Seok Jeong

Dong-jin Lee

Kye-Hyun Kyung

Nak-Won Heo

Jin-Soo Park

Seong-soo Lee

Young-Hoon Kim

Heung-bae Lee

Byong-mo Moon

Jae-Jin Lee

Ho-Young Song

Kang-Seol Lee

Soo-Young Jang

Yong-Hun Kim

Young-Suk Seo

Seong-Eon Park

Jung-June Park

Chan-young Jeong

Jun-Gi Jo

A method of adjusting the size, position, or arrangement of a UI and a user terminal using the method are disclosed. The user terminal includes a display unit for displaying a UI, and a UI control unit configured to display the UI on the display unit with at least one of a position, size, and arrangement of the UI adjusted according to an input by a user.

Method of adjusting an UI and user terminal using the same

A system for linking and controlling terminals is disclosed. A user terminal includes an image unit configured to output image data corresponding to a first image to be shared with a receiving terminal viewed by a user of the user terminal, and a signal unit configured to transmit the image data outputted from the image unit and position information of a touch input touching the user terminal to the receiving terminal. Here, the position information is position information of the touch input touching the user terminal at a preset pressure level or lower or with a preset contact area or smaller, and is displayed on the receiving terminal in an image form.

System for linking and controlling terminals and user terminal used in the same

A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Phase detector, phase-frequency detector, and digital phase locked loop

A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.

Signal transmission circuit

A system for linking and controlling terminals includes a user terminal that includes an image unit configured to output image data to be shared with a receiving terminal larger than the user terminal, and a signal unit configured to transmit an image signal and a control signal to the receiving terminal, the image signal having the image data outputted from the image unit, and the control signal including position information of a touch means near the user terminal. An image representing the position information of the touch means is displayed on the receiving terminal to enable a control of the user terminal by way of the receiving terminal viewed by a user of the user terminal.

A method of adjusting the size, position, or arrangement of a UI and a user terminal using the method are disclosed. A method of adjusting a UI on a user terminal includes: displaying a first UI on a display unit of a user terminal; and displaying a second UI having a reduced size from that of the first UI, in the event that a touch means touching an adjustment area positioned on at least one of an upper side, a lower side, a left side, and a right side of the display unit is moved in a particular direction while maintaining contact, where the adjustment area is positioned within a preset distance from a bezel of the user terminal, and the position where the second UI is displayed is determined according to a touch position of the touch means.

A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal.

Dual mode satellite signal receiver and method thereof

A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

Clock data recovery apparatus

An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Integrated circuit memory devices including mode registers set using a data input/output bus

A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

Integrated circuit memory devices that support selective mode register set commands

A subharmonic mixer, including an amplification unit for amplifying an input signal using at least one pair of amplification devices connected in parallel and a mixing unit for mixing the amplified signal with local oscillation signals from local oscillators is provided. The mixing unit performs switching over the amplification devices and at least four pairs of switching devices connected in parallel with each other, two pairs of switching devices being connected in parallel with each other and performing switching over one amplification device. The switching devices are supplied with local oscillation signals having different phases respectively, and two switching devices forming a pair are connected in parallel with each other and supplied with local oscillation signals having a 180&#xb0; phase difference therebetween. Accordingly, the switching stage is formed with one stage, the operation is enabled with low-voltage power supplies, and noise performance, linearity, and gain are enhanced.

Subharmonic mixer capable of reducing noise and enhancing gain and linearlty

Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Growing community of inventors

Seoul, South Korea

Chang-Sik Yoo