Samsung Electronics Co., Ltd.

Chang-sik Kim

Seong-woon Booh

Young-Dae Lee

Jin-ho Park

Che-Heung Kim

Soo-Hwan Kim

Byong-Kwon Lee

Seok-Won Hwang

Hyun-Dong Kim

Che-heung Kim

Ju-ho Kim

Dong-ryul Ryu

Tae-hyung Lim

Kyeong-seob Moon

Young-uk Chang

Byung-mook Choi

Young-ho Seo

According to example embodiments, a substrate for a power module includes a first part, a second part, and a third part on a same surface of an underlying part of the substrate. The first part, the second part, and the third part may be spaced apart from each other, electrically insulated from each other, and not directly contacting each other. The third part may surround the first part and the second part. A first element module may be on the third part. The first part, the second part, and the third part may be conductive.

Substrate and terminals for power module and power module including the same

According to example embodiments, a substrate for a power module includes first to third parts spaced apart from each other, where the third part surrounds the first and second parts, and a conductive layer on the first to third parts. A terminal of a first polarity is connected to the first part, and a terminal of a second polarity is connected to the second part. The first and second terminals may be spaced apart from each other and each have a coupling part, a body, and a contact part. The bodies of the first and second terminals may overlap each other. A power module may include the substrate.

A test circuit of a semiconductor memory device for performing a test in cooperation with a tester having a plurality of input/output pins connected to a plurality of input/output lines. The test circuit may include a first comparing unit adapted to compare, on a bit-by-bit basis, read data that may be read from memory cells corresponding to an address with expected data, and to output the comparison results as first comparison signals, a second comparing unit adapted to perform a logic operation on the first comparison signals and to generate a flag signal when determining a failure of at least one of the memory cells on the basis of the operation result, and a storage unit adapted to store the first comparison signals in response to the flag signal.

Test circuits of semiconductor memory device for multi-chip testing and method for testing multi chips

An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.

Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device

A plasma processing apparatus such as a plasma etching apparatus, which is not subject to arcing to the gas distributor plate which is caused by secondary potentials generated by polymers adhering to a gas distribution plate. The gas distribution plate is electrically isolated from the ground electric potential, and does not have any polarity. The gas distribution plate may be formed of an insulating material. Furthermore, a support plate may be adapted to fix the gas distribution plate to a chamber of the apparatus in such a manner that the gas distribution plate is detachably coupled with the support plate. Thereby, it is easier to separate the gas distribution plate from the apparatus to remove the accumulated polymers during the plasma process.

Plasma processing apparatus protected from discharges in association

Growing community of inventors

Suwon-si, South Korea

Chang-sik Kim