Marvell International Limited

Chang Shu

Fei Sun

Sean Lee

Heng Tang

A system including a first circuit and a second circuit. The first circuit includes a multiplier array to receive a first operand and a second operand and generate a plurality of outputs, an adder array to receive the plurality of outputs and generate a partial product of the first operand and the second operand including partial sums and carry bits, which are stored in a plurality of register arrays. The second circuit generates the product of the first operand and the second operand by implementing a two-stage reduction of the partial product of the first operand and the second operand. A first stage includes rearranging the partial sums and carry bits as two multi-bit integers. A second stage includes generating a plurality of multi-bit integers based on the two multi-bit integers, and generating the product of the first operand and the second operand based on the plurality of multi-bit integers.

Prime field elliptic cryptography processor

A system including a processor, a field addition circuit, and a field multiplication circuit. The processor is configured to execute instructions for performing elliptic curve operations on data. The elliptic curve operations include field operations performed in a prime field. The field addition circuit is configured to perform a field addition on the data in the prime field in response to the instructions requiring the field addition. The field multiplication circuit is configured to perform a field multiplication on the data in the prime field in response to the instructions requiring the field multiplication.

Prime field elliptic curve cryptography processor

A system includes an interface module, an addressing module, and a multiplier module. The interface module is configured to (i) receive operands and configuration data for a Rivest-Shamir-Adleman (RSA) operation or an Elliptic Curve Cryptography (ECC) operation, and (ii) control access to a random access memory (RAM). The addressing module is configured to allocate memory space within the RAM for storage of the operands. The multiplier module includes a Montgomery multiplier configured to perform Montgomery multiplication operation for both the RSA operation and the ECC operation.

Multiple algorithm cryptography system

A system to perform Montgomery multiplication includes a first multiplier array configured to multiply w bits of an operand X by W bits of an operand Y, where w and W are integers and w is less than W. A second multiplier array is configured to multiply w bits of an operand Q by W bits of a modulo M. An adder array is configured to add outputs of the first and second multiplier arrays to generate a sum. A partial sum array is configured to store a left portion of the sum. A memory is configured to store a right portion of the sum. Q computation logic includes a lookup table and a half-multiplier that compute W bits of the operand Q sequentially in cycles or cycles. The W bits of the operand Q are stored in the fourth buffer for use by subsequent W&#xd7;W operations.

Low cost and high speed architecture of montgomery multiplier

Prime field elliptic curve cryptography processors are provided, having corresponding methods and computer-readable media. The processors comprise a prime field circuit comprising a first memory configured to store data, and an arithmetic logic unit (ALU) circuit configured to perform prime field operations upon the data; and a curve operation processor comprising a second memory configured to store instructions, and a controller configured to execute the instructions; wherein the instructions include instructions for performing curve operations upon the data, wherein the curve operations require performing the prime field operations upon the data; and wherein the instructions for performing the curve operations cause the ALU circuit to perform the prime field operations.

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Chang Shu