Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang-Sheng Liao

Wen-Ting Chu

Kuo-Chi Tu

Chih-Yang Chang

Hsia-Wei Chen

Chin-Chieh Yang

Sheng-Hung Shih

Jen-Sheng Yang

Manish Kumar Singh

Chi-Tsai Chen

Chia-Chung Chen

Shu Fang Fu

The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.

Method and apparatus for reading RRAM cell

In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.

The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.

A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

High voltage metal-oxide-metal (HV-MOM) device, HV-MOM layout and method of making the HV-MOM device

A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor.

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Zhudong, Taiwan

Chang-Sheng Liao