Industrial Technology Research Institute

Sunplus Technology Co., Ltd.

First International Computer, Inc.

Chang-Sheng Chen

Chin-Sun Shyu

Uei-Ming Jow

Ying-Jiunn Lai

Chang-Lin Wei

Min-Lin Lee

Wei-Ting Chen

Ching-Liang Weng

Cheng-Hua Tsai

Shinn-Juh Lay

Shinn-Juh Lai

Kuo-Chiang Chin

Li-Chi Chang

Syun Yu

Chun-Kun Wu

Chang-Chih Liu

Yung-Chung Chang

Pei-Shen Wei

Yu-Min Lin

Sheng-Tsai Wu

Chao-Chuang Mai

Chin-Hui Chen

Ang-Ying Lin

Chih-Ping Cheng

Po-Kai Chiu

Meng-Sheng Chen

Chun-Chi Lin

Yu-Yu Sung

Wen-Hung Liu

Pel-Shen Wei

Chun-Nan Li

Wei-Ming Jow

Guo-Shu Huang

Meng Sheng Chen

Chiung-Sui Liu

Chia-Sheng Chiang

An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

Integrated antenna package structure

An antenna array is provided, which may include a connection portion and a plurality of antenna units. The antenna units may be disposed on the two sides of the connection portion respectively. The proximal end of each of the antenna units may be connected to the connection portion and the distal end of one or more of the antenna units may be grounded. The length of each of the antenna units may be less than or equal to &#xbc; wavelength of the operating frequency of the antenna array, and the distance between any two adjacent antenna units may be less than or equal to &#xbd; wavelength of the operating frequency of the antenna array.

Antenna array and collision avoidance radar having the same

A method and a system, for offsetting measurement of machine tool, includes following steps. A tool seat is chosen, a first coordinate is set based on a first datum mark of the tool seat. There is a total tool seat assembling length in between the first datum mark and the tool seat. A tool is chosen, assembled in the tool seat, and includes a total tool length. A second coordinate is set based on a second datum mark of a measuring unit. The tool seat is moved to make a machining end of the tool contact with the second coordinate to obtain a relative total length in between the first and the second coordinate. The total tool length subtracts from the relative total length equals an assembled offset length. The total tool seat assembling length subtracts from the relative total length equals and obtains a tool assembling length.

System and method for offsetting measurement of machine tool

An antenna having a signal feeding structure, an antenna conductor coupled to the signal feeding structure and forming a slot in the antenna conductor. A closing portion capacitively closing the at least one slot at a mechanically open end of the slot.

Antenna with slot

The invention is directed to inter-helix inductor devices. The inter-helix inductor device includes a dielectric substrate. An input end is disposed on the first surface of the dielectric substrate. A clockwise winding coil has one end connecting to the input end and at least one winding turn through the dielectric substrate. A counter clockwise winding coil includes at least one winding turn through the dielectric substrate, wherein the clockwise and counter clockwise winding coils are connected by an interconnection. An output end is disposed on the dielectric substrate, connects one end of the counter clockwise winding coil, and is adjacent to the input end.

Inter-helix inductor devices

A three-dimensional inductor is provided. The three-dimensional inductor is disposed in a multi-layered substrate. The multi-layered substrate includes at least a dielectric layer and at least two metal layers. The three-dimensional inductor includes a first coil and a second coil. The second coil is electrically connected to the first coil. The first coil is on a first plane and formed on a first metal layer. The second coil is on a second plane and disposed in a variety of dielectric layers and metal layer. The first plane is not parallel to or is vertical to the second plane such that the magnetic field generated by the first coil and the magnetic field generated by the second coil are not parallel to each other or are vertical to each other.

Three dimensional inductor

Radio-frequency identification (RFID) tag antenna, tags and communications systems using the same are presented. The RFID tag antenna includes a patterned conductive loop having a plurality of longitudinal conductive sections and a pair of transverse conductive sections connecting to each end of the longitudinal conductive sections to serve as a matching network. A pair of extended conductive arms is electrically connected to the patterned conductive loop via two nodes. A bonding pad with an RFID chip disposed thereon is arranged at the central area of the pair of extended conductive arms.

Radio-frequency identification (RFID) antenna, tags and communications systems using the same

An inductor device comprising a first conductive pattern on a first layer of a substrate, a second conductive pattern on a second layer of the substrate, and a first region between the first layer and the second layer through which at least one hole is coupled between the first dielectric layer and the second dielectric layer, wherein a magnetic field induced by at least one of the first conductive pattern or the second conductive pattern at the first region is more intensive than that induced by at least one of the first conductive pattern or the second conductive pattern at a second region between the first conductive layer and the second conductive layer.

Inductor devices

A system for processing a television (TV) picture-out-picture (POP) includes a line buffer, a first multiplexer, an image processing engine, a scaling engine and a timing generator. The line buffer receives partial pixels of a first picture and partial pixels of a second picture. The first multiplexer selects the partial pixels of the first and second picture as an output. The image processing engine performs an image processing on the partial pixels output by the first multiplexer to thereby produce processed pixels. The scaling engine performs a scaling operation on the processed pixels to thereby produce scaled pixels. The timing generator produces a timing signal for the image processing engine and the scaling engine and produces enable signals respectively for the first picture and the second picture. The image processing engine and the scaling engine process the partial pixels of the first or second picture in multiplexing.

System and method for processing a television picture-out-picture

A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Mirror image shielding structure

A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Multi-functional composite substrate structure

A capacitor structure is provided. In the capacitor structure, a signal electrode plate and an extension ground electrode plate are disposed on the same plane to form a co-plane capacitor structure. Due to slow wave characteristic, the resonance frequency of the capacitor structure is effectively raised and the capacitor structure may be applied in high frequency.

Capacitor structure with raised resonance frequency

A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.

High frequency and wide band impedance matching via

A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.

Circuit board with embedded components and manufacturing and measuring method thereof

A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Growing community of inventors

Taipei, Taiwan

Chang-Sheng Chen