Samsung Electronics Co., Ltd.

Chang-seok Kang

Jung-Dal Choi

Young-Woo Park

Jong-Sun Sel

Sang-Hun Jeon

Sung-Il Chang

Ju-Hyung Kim

Kohji Kanamori

Yong-Seok Kim

Jae-Duk Lee

Chang-Sup Lee

Kyung-Hwan Lee

Won-Seok Jung

Jong-won Kim

Kee-won Kwon

Jo-young Park

Se-mee Jang

Chang-Hyun Lee

Jae-Goo Lee

Jun-Hee Lim

Byeong-In Choe

Yoo-Cheol Shin

Jang-Sik Lee

Vie-Na Kim

Yong-Hoon Son

Ki-Nam Kim

Kyung-Hyun Kim

Young-wook Park

Cha-young Yoo

Jung-dal Choi

Hong-bae Park

Jin-Soo Lim

Woong-hee Sohn

Jin-taek Park

Young-suk Kim

Phil-Ouk Nam

Yeon-Sil Sohn

Doo-sup Hwang

Jin-I Lee

Won-Bong Jung

Kwang-Chul Park

Ju-hyung Kim

Min-Yeong Song

Byeong-Ju Kim

Min-Yong Lee

Sang-Woo Jin

Jin-soo Lim

A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

Vertical semiconductor device

In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

Method of writing data in nonvolatile memory device, with divided subpages or subblocks, and method of erasing data in nonvolatile memory device with divided subpages or subblocks

A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

Vertical semiconductor devices and method of manufacturing the same

A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

Vertical semiconductor devices

A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole. The second channel hole may extend through the second gate patterns and expose a second portion of the substrate on the second region of the substrate, and the second channel hole may be disposed within an area of the first opening in a plan view, wherein the first opening has a larger area than the second channel hole in a plan view. The second semiconductor pattern may be at a lower portion of the second channel hole.

Methods of manufacturing vertical semiconductor devices

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

Non-volatile memory device

A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Nonvolatile memory device and a method for fabricating the same

A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.

Vertical memory devices and methods of manufacturing the same

A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps

A nonvolatile memory device includes: a plurality of cell strings disposed on a substrate, wherein at least one of the plurality of cell strings comprises a plurality of cell transistors and at least one ground select transistor stacked in a direction substantially perpendicular to the substrate, and the substrate and a channel region of the plurality of cell strings have a same conductivity type; a substrate bias circuit configured to provide an erase voltage to the substrate in an erase operation; and a ground select line voltage generator configured to provide a ground select line saturation voltage to the at least one ground select transistor in the erase operation.

Nonvolatile memory device and an erase method thereof

A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.

Methods of manufacturing vertical structure nonvolatile memory devices

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.

Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices

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Seongnam-si, South Korea

Chang-seok Kang