Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Chang Reol Kim

Jong Moon Choi

Jong-moon Choi

Young Jin Song

Yong Kwon Kim

A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.

Method for fabricating a thin film transistor with the source, drain and

A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.

Transistor fabrication method

A method of forming a metal line structure for use with a semiconductor device includes the steps of: preparing a semiconductor substrate; forming a first line on the semiconductor substrate; forming a plug pattern on the first line; forming at least one insulating layer on an exposed surface of the first line and on the plug pattern; planarizing the insulating layer and, simultaneously, removing the plug pattern to form a contact hole which exposes at least a portion of the first line; and forming a second line in the contact hole such that the second line is configured to couple with the first line.

Growing community of inventors

Chungcheongbuk-do, South Korea

Chang Reol Kim