Samsung Electronics Co., Ltd.

Hyundai Motor Company

Chang-Rae Kim

Min-Chul Chung

Jong-Yul Park

Sang-jib Han

Seung-Keun Lee

Chul-Ho Lee

Hee-Choul Park

Jong-young Kim

Sang-Jib Han

Hyun-Duk Cho

Pyung-moon Zhang

Choong-keun Kwak

Dong-Chung Kang

Heui-Chul Park

Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Memory device and system with cyclic, ECC-corrected bootloading operation during voltage bring up

A memory system is provided which comprises a main memory that stores main data and reference data; a first storage that stores the reference data; and a controller that accesses the reference data from the main memory upon receipt of a power up signal, and loads the main data into a second storage when the reference data retrieved from the main memory is tested to be the same as the reference data in the first storage. A method is also provided for booting a nonvolatile memory, comprising prestoring in a main memory a boot code and a reference data; prestoring the reference data in a register; accessing the reference data from the main memory when power is turned on; comparing the reference data in the register against the reference data accessed from the main memory; and loading the boot codes into a boot RAM if the reference data in the register is the same as the reference data accessed from the main memory and if not the same, repeating accessing and comparing the reference data from the main memory against the reference data in the register.

System and method for accessing vital data from memory

A defect address storing circuit for a semiconductor memory device comprises a plurality of fuse pairs formed in a fuse region and a plurality of transistors formed in a transistor region outside the fuse region. The plurality of fuse pairs and the plurality of transistor pairs are arranged to form a continuous current path through at least one fuse in each of the plurality of fuse pairs, and through at least one transistor in each of the plurality of transistor pairs.

Defect address storing circuit for semiconductor memory device

A memory system includes a flash memory device and an interface device. The flash memory device includes a one-time programmable block where protection data information is stored in a predetermined region, and the interface device includes a register for storing one-time programmable lock status information to indicate whether the one-time programmable block is programmed. When a program/erase command is applied externally in a one-time programmable mode, the interface device having the one-time programmable lock status information indicates whether the one-time programmable block is programmed. If the one-time programmable lock status information indicates that the one-time programmable block is programmed, the interface device cuts off an external access to the one-time programmable block.

Memory system having flash memory where a one-time programmable block is included

Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.

Method and apparatus for refreshing semiconductor memory

Refresh-type memory with zero write recovery time and no maximum cycle time

A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete. At a convenient time after the end of the external write command (e.g., during the next external write command), a short pulsed write operation transfers the data to the memory cell array.

A power supply voltage detecting circuit for preventing a current from being supplied to a chip in a stand-by state when a chip is not in operation, which is capable of being used even at a low power supply voltage. The power supply voltage detecting circuit for operating at a low power supply voltage includes a power supply voltage node whose output voltage varies as a function of an external power supply voltage, and a reference voltage node having a given voltage characteristic in accordance with the external power supply voltage. The circuit comprises: a differential amplifier which includes first and second N-type transistors and first and second P-type transistors, for comparing output voltages of the power supply voltage node and the reference voltage node; a fifth N-type transistor which has a gate connected with the reference voltage node; third and fourth N-type transistors, each connected with the fifth N-type transistor and having a gate regulated by a chip selection signal; a sixth N-type transistor having a gate regulated by an inverted chip selection signal; and a NOR gate, for finally outputting an output voltage of a logic low state at all times when a chip is in a stand-by state.

Power supply voltage detecting circuit for use in semiconductor memory

A redundancy decoding circuit for a semiconductor memory device is shown which includes a comparator which decodes and outputs a redundant memory cell address in response to an address signal, where the comparator includes internal fuses that are coupled to an output terminal of the comparator and which can be selectively cut in order to determine the redundant memory cell address. The redundancy decoding circuit also includes a driving unit which supplies a driving current to the output terminal of the comparator in response to a switching control signal. A pulse generator generates a power up pulse having a predetermined width responsive to power up of the redundancy decoding circuit. A switching control signal generator, which includes a master fuse connected in series with a switching element, generates the switching control signal at a predetermined voltage level in response to the power up pulse generated by the pulse generator even when the master fuse is incompletely cut.

Redundancy decoding circuit for a semiconductor memory device

A method for controlling engine ignition for use in a engine system wherein the engine system includes a plurality of cylinders and a crank shaft coupled to the cylinders, comprises the steps of: detecting a rotation angle of the crank shaft to thereby generate crank angle pulses, generating a cylinder pulse for identifying each of the cylinders, detecting the rising edge and the falling edge of each of the cylinder pulses to identify each of the cylinders, initializing the counting of the number of crank angle pulses, determining an ignition timing for each of the cylinders to thereby obtain an integer part and a decimal part thereof, comparing the integer portion with the number of crank angle pulses, converting the decimal portion into an ignition time; and generating an ignition signal at the ignition time when the number of crank angle pulses coincides with the integer part.

Method for controlling engine ignition

A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.

Data buffer circuit with delay circuit to increase the length of a

A semiconductor memory device has normal memory blocks and redundant memory blocks for storing data therein. To elevate the redundancy efficiency, the memory device includes a number of normal block selectors for selecting the normal blocks, a number of redundant decoders for sensing a redundant mode on a basis of address signals provided thereto from an address buffer, a block selection decoder for generating a block selection signal by receiving an external address signal shaped, and a redundancy combining signal generator for generating a normal block selection signal and a redundant block selection signal by receiving output of the block selection decoder and output of the redundant decoder.

Growing community of inventors

Yongin-si, South Korea

Chang-Rae Kim