Mediatek Corporation

Industrial Technology Research Institute

Chang-Po Ma

Hong-Ching Chen

Yuan-Chin Liu

Yung-Chi Yang

Che-Kuo Hsu

Jui-Tse Lin

Yu-Hsun Chen

Ta Hsing Liu

Yi-Hsin Yu

Sun-How Jiang

A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Scheduler for deciding final output queue by selecting one of multiple candidate output queues and related method

Disclosed is a clock generator for generating a target clock signal, which includes: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the control circuit, for delaying the reference clock signal according to the delay selecting signal to generate a delayed reference clock signal; and a clock gating unit, coupled to the delay module and the control circuit, for receiving the delayed reference clock signal and the clock enable signal, and for passing the delayed reference clock signal according to the clock enable signal, to generate the target clock signal.

Clock generator, pulse generator utilizing the clock generator, and methods thereof

A clock generator for generating a target clock signal, comprising: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the control circuit, for delaying the reference clock signal according to the delay selecting signal to generate a delayed reference clock signal; and a clock gating unit, coupled to the delay module and the control circuit, for receiving the delayed reference clock signal and the clock enable signal, and for passing the delayed reference clock signal according to the clock enable signal, to generate the target clock signal.

A clock generator for generating a first target clock signal includes: a control circuit, receiving a reference clock signal, and for generating a first clock enable signal and a first delay selecting signal according to the reference clock signal; a first clock gating unit, coupled to the control circuit, for receiving the reference clock signal and the first clock enable signal, and for passing the reference clock signal according to the first clock enable signal to generate a first clock gated signal; and a first delay module, coupled to the first clock gating unit, for delaying the first clock gated signal according to the first delay selecting signal to generate the first target clock signal.

A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

Delay circuit and related method thereof

A delay circuit includes a first delay module, a delay measurement unit and a fault judge unit. The first delay module has a first delay circuit with at least one delay stage. The delay measurement unit is used for measuring a first delay amount and a second delay amount of the first delay chain respectively corresponding to a first number and a second number of delay stages. The fault judge unit is used for determining if the first delay chain has delay faults or not according to the first and second delay amounts.

Delay circuit and related method

Disclosed are a method and device of converting data words into code words. This method inserts 2p guided bits before inputting each set of data words, performs a pre-defined operation, and generates 2data sequences with different guided bits. It chooses q data sequences from the 2data sequences for coding, performs a run length limited (RLL) coding with a coding rate m/n, and generates q (d, k) constrained code word sequences. Finally, an optimal (d, k) constrained code word sequence is selected from the q (d, k) constrained code word sequences. The device reduces the circuitry of the RLL coding applied guided scrambling without losing the control of direct current and low frequency components.

Method and device of converting data words into code words

A state modulation method and an apparatus for inserting state control codes are provided. To overcome the problems of inefficient control on direct current and low frequency component in conventional state modulation techniques, the disclosed method inserts state control codes in a state modulation method to increase the probability for selection. With multi-level characteristics, the inserted state control codes can provide a plurality of sets of different signals for selection during coding. Thereby, the direct current and low frequency components can be well controlled.

Growing community of inventors

Hsinchu, Taiwan

Chang-Po Ma