Goldstar, Co., Ltd.

Chang P Lee

Jong Soo Choi

Ki Hong Song

Ki Hwan Song

A B-frame processing apparatus including a motion compensation apparatus in the unit of a half pixel for an image decoder adapted to a video appliance such as HDTV. According to the apparatus, motion compensation in the unit of a half pixel is performed in real time with respect to the image having been motion-compensated by frame memories, the half pixel motion-compensated image data is added by an adder to the image data provided from a restoring section, and then the added image data is provided to the frame memories for performing motion compensation in the unit of a pixel, while the order of the input image is adjusted corresponding to the display order of the final output image.

B-frame processing apparatus including a motion compensation apparatus

A B-frame processing apparatus including a motion compensation apparatus in the unit of a half pixel for an image decoder adapted to a video appliance such as HDTV. According to the apparatus, motion compensation in the unit of a half pixel is performed in real time with respect to the image having been motion-compensated by frame memories, the half pixel motion-compensated image data is added by an adder to the image data provided from a restoring section, and then the added image data is provided to the frame memories for performing motion. compensation in the unit of a pixel, while the order of the input image is adjusted corresponding to the display order of the final output image.

A coefficient generation apparatus for a variable length decoder, capable of simplifying its circuit arrangement and reducing a processing time required to decode run-length signals and thus recover them to have actual coefficients. The apparatus comprises an absolute address generation circuit for generating an absolute address, based on a run signal from a run/level decoder, a memory control circuit for outputting the run signal of the run/level decoder and an output signal of the absolute address generation circuit and controlling outputting of a level from the run/level decoder, a first-in and first-out (FIFO) memory for storing the level and address outputted from the memory control means, and a coefficient generation circuit for outputting required level at addresses whose level values are transferred and zero at the remaining addresses, based on the run value from the FIFO memory, and thus generating a predetermined number of coefficients per block.

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Seoul, South Korea

Chang P Lee