Global Unichip Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang-Ming Liu

Igor Elkanovich

Yung-Sheng Fang

Pei Yu

Shih-Hua Hsu

Chien-Hao Lin

Tsung-Ju Hsieh

Hui-Ting Yang

Ting-Hao Wang

Amnon Parnass

Ting-Chin Cho

Teng-Hui Lee

Chia-Chien Tu

Ning-Chun Hsu

Pi-Tsan Lo

Chen-Ya Sun

Ko-Yun Weng

A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Communication system between dies and operation method thereof

A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.

Electronic system, integrated circuit die and operation method thereof

A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.

Frame decoding circuit and method for performing frame decoding

A method for utilizing a probe card includes steps as follows. Providing a probe card having three alignment marks on a reference plane of a circuit board; moving the circuit board to be oriented to a wafer-loading plane of a wafer stage with the reference plane; determining whether a geometric plane defined by the alignment marks is parallel to the wafer-loading plane; and when the geometric plane is not parallel to the wafer-loading plane, adjusting a levelness of the circuit board until the reference plane is parallel to the wafer-loading plane.

Method, system for utilizing a probe card, and the probe card

A probe card and a testing method are disclosed herein. The probe card includes a plurality of probe sets arranged as a testing unit. The testing unit is configured to test a plurality of dies in a test region on a wafer, and to move m unit along a first direction and n unit along a second direction when the test complete so as to test the next test region, in which m and n are integers.

Probe card and testing method

A brightness calibration method used in an optical detection system includes a single source illuminator and a probe card. The single source illuminator is configured to illuminate the probe card. The probe card has a plurality of detection sites. The brightness calibration method includes: sequentially detecting brightness values at the detection sites through one of a plurality of diffusers by a sensing chip; sequentially detecting transparencies of the diffusers at one of the detection sites by the sensing chip; and selecting and respectively disposing the diffusers corresponding to larger ones of the transparencies over the detection sites corresponding to smaller ones of the brightness values, and selecting and respectively disposing the diffusers corresponding to smaller ones of the transparencies over the detection sites corresponding to larger ones of the brightness values.

Brightness calibration method used in optical detection system with a plurality of diffusers

An optical inspection fixture includes a first bracket, a second bracket and at least one loading surface. The first bracket is provided with at least one first arm. The second bracket and the first bracket are separated from each other so as to define a light traveling path that lights can go through. The second bracket is provided with at least one second arm which is separated from the first arm. The loading surface is between the first bracket and the second bracket, and connected to at least one of the first arm and the second arm, and the loading surface is used to carry an optical conversion element.

Optical inspection device and optical inspection fixture thereof

A register system includes a register unit and a control unit. The register unit is utilized for storing a first data packet, wherein the register unit has an end flag. The control unit is coupled to the register unit, for indicating a designated information and an end position of the first data packet by using the end flag.

Growing community of inventors

Hsinchu County, Taiwan

Chang-Ming Liu