Lg Semicon Co., Ltd.

Chang-Man Khang

Tae-Hyoung Kim

Jae-Goo Lee

Ha-Soo Kim

Chang-Jin Lee

The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.

Semiconductor memory device with improved sense amplifier driver

The present invention relates to a charge pump circuit for memory device, more particularly to a circuit charging cell capacitors or bitlines up to a full level of power supply voltage by means of compensating for the loss caused by the threshold voltages of memory transistors with the elevated potential higher than the power supply voltage. The present invention includes an elevated potential terminal connected to an output capacitor, a level monitor connected to said elevated potential terminal wherein a certain range of voltage is divided into a plurality of voltage level intervals, and the level monitor generates a plurality of pumping enable signals corresponding to a plurality of the voltage level intervals, and a plurality of the pumping enable signals have different activated time one another, and the level monitor activates the pumping enable signals corresponding to the voltage level intervals to which the elevated potential belongs among the voltage level intervals by means of detecting the elevated potential, a pulse generator connected to the level monitor wherein the pulse generator generates a pulse signal, and wherein at least one of the pumping enable signals is activated, and a plurality of charge pump modules connected to the pulse generator wherein the charge pump modules are enabled by the pumping enable signals, and wherein the charge pump modules supplies the output capacitor with electric charge with pumping operation by the pulse signals.

Charge pump circuit for memory device

A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.

Semiconductor memory having bitline precharge circuit

A word line driving circuit for a semiconductor memory is provided that drives a corresponding word line of a first number of word lines coupled to a plurality of memory cells based on a memory address signal generated from a more significant controller. The memory cells have a matrix form of rows and columns and the first number of word lines are divided into a second number of word line groups. The word line driving circuit includes a second number of word line group driving circuits each respectively coupled to one of the second number of word line groups to drive one of the word lines in the word line group selected by a control signal. A word line selecting circuit determines which of the second word line groups contain the corresponding word line to be driven using the memory address signal and generates the control signal for the corresponding word line group driving circuit.

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Kyonggi-do, South Korea

Chang-Man Khang