Macronix International Co., Ltd.

Novatek Microelectronics Corp.

Industrial Technology Research Institute

Chang-Lun Chen

Albert C Sun

Chee-Horng Lee

Hsiao-Ming Huang

Tsui-Chin Chen

Ho-Lin Wang

Chui-Hsun Chiu

Dze-Chang Wang

Wei-Wen Chang

Allen S Wang

Meng-Hsiu Wei

Chun-hao Li

An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

Image processing method and device thereof

A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed. Bridge logic produces an output video stream which has an output frame rate matching the input frame rate, and in which the output frame has at least one of a variable number of pixels per line within an output frame, and/or a variable number of lines per frame among output frames in a set of more than one output frames.

Methods and apparatus for bridging different video formats

An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed. The processor and ICP code are responsive to an in-circuit programming update command to write a copy of the in-circuit programming set from a first memory array to a second memory array, and to cause the in-circuit programming to execute the in-circuit programming set from the second memory array to program the non-volatile memory cells of the first memory array with data from the external port.

Processor with embedded in-circuit programming structures

An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself; as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed. The processor and ICP code are responsive to an in-circuit programming update command to write a copy of the in-circuit programming set from a first memory array to a second memory array, and to cause the in-circuit programming to execute the in-circuit programming set from the second memory array to program the non-volatile memory cells of the first memory array with data from the external port.

System for logic extraction from a layout database

An architecture for an integrated circuit with in-circuit programming includes a microcontroller on an integrated circuit and one or more banks of non-volatile memory which store instructions, including an in-circuit programming (ICP) set of instructions. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a device external to the integrated circuit and uses data obtained in the exchange to update software for the microcontroller. Portions of the ICP code which are likely to change between different application environments are stored in reprogrammable flash memory cells. Other portions of the ICP code, which are not likely to change between different application environments, are stored in space-efficient mask ROM memory cells. In this way, the ICP system can be flexibly adapted to different application environments, while conserving on silicon area occupied the ICP system.

In-circuit programming architecture with ROM and flash memory

A method and system is disclosed for efficiently transferring a sequence of data words from an I/O device to sequential addresses in a main memory via an I/O bridge. The sequence of data words to be transferred includes one or more subsequences of data words. Each subsequence of data words include only data words destined to addresses of the main memory in which data words of only one data line are stored. The I/O bridge has control logic for receiving a first subsequence of data words corresponding to a currently owned data line and for claiming ownership in one or more of the very next data lines corresponding to the next subsequences of data words to be transferred from the I/O device. The I/O bridge also has a buffer memory for storing a subsequence of the sequence of data words received from the I/O device. The control logic maintains in a pre-own tag array a list of the data lines in which ownership has been successfully claimed and a list in a buffer tag array of storage locations in the buffer memory allocated to receiving data words of particular subsequences of the sequence of data words from the I/O device.

Growing community of inventors

Hsinchu, Taiwan

Chang-Lun Chen