Realtek Semiconductor Inc.

Chang-Lien Wu

Jin-Ru Chen

Po-Wei Liu

Chun-Feng Liu

Huan-Tang Hsieh

Hsin-Min Wang

Jia-Jia Cai

Jen-Che Tsai

Jian-Yin Zhu

Chih-Ching Wang

Yin-Hsin Tsai

An Ethernet connection method and an Ethernet device thereof are provided. The Ethernet connection method and the Ethernet device can transmit data with Error Correction Code (ECC) even with only one twisted pair or two twisted pairs when the Ethernet wire cannot transmit with the full four twisted pairs.

Ethernet connection method and ethernet device thereof

A data aggregation-distribution apparatus includes a plurality of port route units and a data processing unit. Every port route unit has a sending buffer and a receiving buffer. The data processing unit has a data aggregation unit and a data distribution unit. The data aggregation unit and the data distribution unit are used to increase the bandwidth of a communication system.

Data aggregation-distribution apparatus, date transmission system and method thereof

A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.

Method for determining integrity of memory

The present invention provides an apparatus and method for bandwidth control used in a network switch controller. The apparatus and method achieve the goals of simplifying circuits and controlling bandwidth precisely by simplification of counting operations required by bandwidth control and a design of dual counters. The apparatus comprises: a first counter; a control logic for executing a operation of adding or subtracting the first counter by one based on an increment/decrement signal and for determining if a packet is allowed to enter a queue of the switch controller based on a value of the first counter; an action device for performing actions of inputting/outputting the packet to/from the queue, wherein the action device comprises a second counter which is increased by one when a byte is inputted, the second counter is reset to zero and generates the increment signal to the control logic when increased to one unit bytes; and a timer for generating the decrement signal to the control logic every unit time. The method employs the above apparatus to input packets and decreases the first counter by one to limit data volume allowed to input during one unit time to one unit bytes.

Apparatus and method for bandwidth control

A method and networking apparatus for providing fault tolerance to memory are disclosed. The networking apparatus contains a first memory for storing host/port relationships, a second memory for indicating the status of the first memory, and a processor coupled to the memories for manipulating the memories. Furthermore, the claimed invention may also include an optional third memory for serving as a secondary site for storing information regarding host/port relationships.

Method and apparatus for providing fault tolerance to memory

A differentiated granularity timing apparatus and a method to provide various flexible timing granularities without requiring much memory space and complex circuit design are disclosed. The differentiated granularity timing apparatus of the present invention comprises a differentiated granularity timing unit, a comparing unit, an adder and a buffer. The buffer is for storing a time value. The comparing unit further comprises a comparator and a plurality of predetermined time interval values stored therein. The comparator is for outputting a control signal according to the time value. The differentiated granularity timing unit further comprises a multiplexer and a plurality of timers. Each timer is for providing a timing signal with different timing granularities respectively. The multiplexer is for outputting one of the timing signals with the corresponding timing granularity according to the control signal.

Timing method and apparatus for digital logic circuits

The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.

Growing community of inventors

Hsinchu, Taiwan

Chang-Lien Wu