Samsung Electronics Co., Ltd.

Chang-Kyu Seol

Jun-Jin Kong

Hong-Rak Son

Pil-sang Yoon

Seong-Hyeog Choi

Young-Geon Yoo

Ki-Jun Lee

Hye-Jeong So

Dong-Whan Lee

Dong-Sup Jin

Jae-Yong Son

Hyun-Seuk Yoo

An apparatus that receives a non-binary polar code through a channel includes a low-complexity decoder and a memory. The low-complexity decoder is configured to selectively calculate first common terms for input symbols in the non-binary polar code other than a first input symbol corresponding to a first target output symbol. The selective calculation uses a lower triangular kernel and log likelihood ratios of the input symbols generated based on a channel characteristic of the channel. The low-complexity decoder is also configured to calculate log likelihood ratios of the first target output symbol using the first common terms and to determine a value of the first target output symbol based on the log likelihood ratios of the first target output symbol. The memory is accessible by the low-complexity decoder and is configured to store the first common terms.

Apparatus that receives non-binary polar code and decoding method thereof

A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

Memory device, memory system, and method of operating the memory system

Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

Method for operating non-volatile memory controller

Provided are a flash memory device, a flash memory system, and methods of operating the same. A method of operating a flash memory system includes selecting memory cells of a flash memory in response to an authentication challenge, programming pieces of input data into the selected memory cells, respectively, reading the selected memory cells and generating and storing control information, dividing the selected memory cells into at least one first region memory cell and at least one second region memory cell based on the control information, and setting read values of the at least one first region memory cell and the at least one second region memory cell as a first value and a second value, respectively, and generating an authentication response in the response to the authentication challenge.

Flash memory device, flash memory system, and methods of operating the same during an authentication challenge

A memory device, a memory system, and an operating method of the memory system is provided. The operating method includes operations of transmitting an authentication request to a memory device using a memory controller; converting the authentication request to a first address using the memory device; processing authentication data that corresponds to the first address and indicates a physical characteristic of the memory device and transmitting the authentication data as an authentication response to the authentication request to the memory controller using the memory device; and verifying whether the authentication response received from the memory device is an authentication response to the authentication request using the memory controller.

Memory device, memory system, and operating method of memory system

A method is provided for determining a deterioration condition of a memory device. The method includes calculating first information corresponding to a number of bits having a first logic value from data obtained by performing a first read operation on target storage region of the memory device using a first reference voltage as a read voltage, and calculating second information corresponding to a number of bits having a second logic value from data obtained by performing a second read operation on the target storage region using a second reference voltage as the read voltage. A deterioration condition of the target storage region is determined based on the first and second information. The first reference voltage is less than a first read voltage by which an erase state of the memory device is distinguished from an adjacent program state, and the second reference voltage is higher than the first read voltage.

Method of determining deterioration state of memory device and memory system using the same

A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to determine a read voltage level compensation value corresponding to a difference between the number of the first state values of the sample data written to the memory and the number of the first state values of the read data read from the memory.

Semiconductor storage device, system, and method

Data is read from memory cells, including at least one victim cell and at least one aggressor cell, using an element graph. Reading the data includes defining function nodes corresponding to probability density functions with respect to a first physical characteristic of the at least one victim cell and a second physical characteristic of the at least one aggressor cell, defining variable nodes corresponding to at least one first data value stored in the at least one victim cell and at least one second data value stored in the at least one aggressor cell, and defining edges connecting the function nodes and the variable nodes.

Memory device and method of reading data from memory device using element graphs

Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.

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Osan-si, South Korea

Chang-Kyu Seol