Hynix Semiconductor Inc.

Samsung Electronics Co., Ltd.

Chang-Kyu Choi

Kyung-Hoon Kim

Sang-Yeon Byeon

Jun-Woo Lee

Dae-Han Kwon

Geun-Il Lee

Yong-Ju Kim

Jun-Ho Lee

Taek-Sang Song

Jun-Ho Park

Sung-Woo Han

Kun-Woo Park

Kwan-Weon Kim

Sun-Gi Hong

Dae-Kun Yoon

Nam-Woo Kim

Hye-Jeong Lee

Hong-Seok Yang

Seong-Woon Kim

Byung-In Yoo

Kwang-Il Hwang

Yill-Myung Yim

Yeun-Bae Kim

Sung-Jung Cho

Jay-Woo Kim

Dong-Geon Kong

A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels.

Semiconductor device

An on-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response to the calibration code; and a reference resistor unit coupled to the calibration resistor unit, and configured to be turned on and off in response to a control signal.

On-die termination device

An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Output circuit of semiconductor device

Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus

A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.

Semiconductor integrated circuit

A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.

Circuit and method for parallel to serial conversion

A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Parallel-to-serial converter

A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up or pull down a predetermined node and compare a voltage of the predetermined node with a reference voltage to generate calibration codes, by using parallel resistor units that are turned on or off in response to the calibration codes. An output driver is configured to terminate a data output node to a pull-up or pull-down level to output data, by using the parallel resistor units. At least one of the parallel resistor units having at least two resistivities includes resistors with different resistivities connected to each other in parallel.

Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device

A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.

Semiconductor memory device

A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

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Gyeonggi-do, South Korea

Chang-Kyu Choi