Samsung Electronics Co., Ltd.

Chang-Kyo Lee

Jung-Hwan Choi

Kyung-Soo Ha

Seok-Hun Hyun

Ki-Seok Oh

Yeon-Kyu Choi

Dae-Sik Moon

Gil-Hoon Cha

Young-Hoon Son

Si-hong Kim

Young-Soo Sohn

Jin-Hoon Jang

Yoo-Chang Sung

Jin-Seok Heo

Ju-Ho Jeon

Wang-Soo Kim

Jin-Sung Youn

Ki-Duk Park

Yoon-Joo Eom

Yong-cheol Bae

Min-Su Ahn

Jun-Ha Lee

Won-young Lee

Bo-bae Shin

A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Memory device adjusting duty cycle and memory system having the same

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Method of controlling on-die termination and system performing the same

A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Memory modules, memory systems and methods of operating memory modules

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Seoul, South Korea

Chang-Kyo Lee