Skhynix Inc.

Chang Kwon Lee

Su Hyun Oh

Myeong Jae Park

Jinhyung Lee

Ji Hwan Kim

Jin Hyung Lee

A semiconductor device comprising: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

Semiconductor device including internal transmission path and stacked semiconductor device using the same

A semiconductor device comprises: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.

Duty correction device including duty correction circuit and semiconductor device including duty correction device

An integrated circuit (IC) chip includes a plurality of interlayer channels; at least one data pad; an identification (ID) generation circuit suitable for generating a chip ID signal by decoding a command/address signal; a first transmission circuit suitable for transferring a plurality of internal data pieces to a transmission path by aligning a plurality of interlayer data pieces respectively transferred from the plurality of interlayer channels according to a plurality of strobe signals while selectively inverting the plurality of interlayer data pieces according to the chip ID signal; and a second transmission circuit suitable for transferring the plurality of internal data pieces from the transmission path to the at least one data pad.

Growing community of inventors

Gyeonggi-do, South Korea

Chang Kwon Lee