Intel Corporation

Chang Kian Tan

Kuljit Singh Bains

Chee Hak Teh

Saravanan Sethuraman

Robert S Chappell

Rohit Bhatia

Gur Hildesheim

Ru Yin Ng

An apparatus is described. The apparatus includes a memory controller having a network interface and a channel interface. The channel interface is to send read, write and refresh commands into a region of a memory. The network interface is to receive memory access requests from a network, wherein the memory requests target the region of the memory. The memory requests are sent into the network by one or more host interfaces. The memory controller has bank refresh logic circuitry. The memory controller has signaling logic circuitry to send a back pressure signal to the one or more host interfaces. The back pressure signal identifies a bank of the region of the memory that is about to be refreshed by the bank refresh logic circuitry. The back pressure signal is to inform the one or more host interfaces that any memory requests that target the bank will not be serviced by the region of memory before the bank begins to be refreshed.

Per bank refresh hazard avoidance for large scale memory

Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Per channel thermal management techniques for stacked memory

An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

Integrated circuits having memory with flexible input-output circuits

In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

Growing community of inventors

Bayan Lepas, Malaysia

Chang Kian Tan