Skhynix Inc.

Chang-Ki Baek

Joon-Woo Choi

A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.

Multi-chip package, system and test method thereof

A semiconductor memory device includes a clock input block suitable for generating first and second internal clocks in response to an external clock, a clock correction block suitable for generating a data clock by correcting a duty ratio of the first and second internal clocks in response to a signal activated in an initial operation mode of the semiconductor memory device, and a data control block suitable for controlling data in synchronization with the data clock.

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Gyeonggi-do, South Korea

Chang-Ki Baek