Skhynix Inc.

Chang Ki Baek

Joon Woo Choi

Saeng Hwan Kim

Mun Seon Jang

Min Wook Oh

Min Ook Kim

Myung Kyun Kwak

Jae Woong Yun

In Tae Kim

A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.

Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same

A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.

Semiconductor memory apparatus operating in a refresh mode and method for performing the same

A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Semiconductor system and semiconductor device

A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.

Semiconductor memory apparatus

A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.

Semiconductor devices

A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.

A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.

Data input circuit of semiconductor apparatus

A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.

A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included.

Fuse information storage circuit of semiconductor apparatus

Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.

Data transmission circuits and system having the same

An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.

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Anyang-si, South Korea

Chang Ki Baek