Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

United Electronics Corp.

Chang-Jyh Hsieh

Jiunn-Ren Hwang

Jui-Tsen Huang

Yung-Cheng Chen

Chue San Yoo

Li-Wei Kung

Chi-Ta Lu

Dong-Hsu Cheng

Peng-Ren Chen

Kuei-Chun Hung

Chien-Ming Wang

A composite mask suitable for multiple-patterning lithographic processes and a multiple-patterning photolithographic process utilizing the mask are disclosed. An exemplary embodiment includes receiving a mask having a plurality of sub-reticles and a substrate having one or more regions. A first sub-reticle of the plurality of sub-reticles is aligned with a first region of the one or more regions. A movement pattern is designated relative to the substrate. A first photolithographic process is performed including exposing the substrate using the mask to form a first exposed area on the substrate. An alignment of the mask relative to the substrate is shifted according to a first direction determined by the movement pattern. A second photolithographic process is performed including exposing the substrate using the mask to form a second exposed area on the substrate such that the second exposed area overlaps the first.

Multiple-patterning photolithographic mask and method

The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Lithography performance check methods and apparatus

An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

Optical proximity correction method

The present invention is provided a method to use a pattern section without extra serif to correct the polygon feature pattern with at least one inner corner. Such that the polygon feature pattern with at least one inner corner can achieve effectively OPC (optical proximity correction) without adding any extra data point. Therefore, the present invention can instead of the conventional serif and achieves the effective OPC. In addition, the mask writing time is also improved since the original feature pattern is divided into a few rectangular-shaped mask writing units or trapeze-shaped mask writing units for regular mask writing, and the inner corner is/are not in the middle of each divided mask writing units. The mask inspection is also simplified and easier to calibration since a simple geometry other than complex serif is used.

Correcting the polygon feature pattern with an optical proximity correction method

A method of correcting an optical mask pattern. A third pattern having a first strip-like pattern and a second strip-like pattern is provided. The first strip-like pattern attaches to the mid-section of the second strip-like pattern. A first modification step is conducted. A pair of assistant patterns is added to the respective sides of the first strip-like pattern to form a first modified pattern. A second modification step is conducted to shrink a portion of the first strip-like pattern to form a second modified pattern. Dimension in the reduced portion of the first strip-like pattern is a critical dimension of a main pattern. A third modification step is conducted using an optical proximity correction method. The second modified pattern is modified to a third modified pattern.

Growing community of inventors

Hsin-Chu, Taiwan

Chang-Jyh Hsieh