Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang Jen-Yuan

Yih Wang

Chia-En Huang

Yi-Ching Liu

Chieh Lee

A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

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Hsinchu, Taiwan

Chang Jen-Yuan