Lg Semicon Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Goldstar Electron Co., Ltd.

Lg Semicon

Chang Jae Lee

Oh Seok Han

Won Suck Yang

Kong Hee Park

Jong Kwan Kim

Nae Hak Park

Gong H Park

Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Wiring for semiconductor device

Wiring for semiconductor device and method for forming the same

A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

Method of forming DRAM matrix of basic organizational units each with

A method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability is disclosed, including the steps of forming an insulating film having a contact hole on a semiconductor substrate; forming a barrier metal layer on the insulating film including the contact hole; and forming a metal line layer on the barrier metal layer with a CVD method using a high density plasma.

Method for forming metal line of semiconductor device

A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Capacitor structure of semiconductor device for high dielectric constant

A method of fabricating a CMOSFET includes the steps of selectively forming first and second conductive type wells in a semiconductor substrate, forming an isolation insulating layer at interface of the first and second conductive type wells, forming a first gate electrode formed of a first conductive type electrode over a predetermined area of the second conductive type well and a second gate electrode successively formed of a second conductive type electrode, a diffusion preventing layer, and the first conductive type electrode over a predetermined area of the first conductive type well, forming sidewall spacers on both sides of each of the first and second gate electrodes, forming second and first conductive type impurity regions under surfaces of the first and second conductive type wells, respectively, at both sides of the first and second gate electrodes and the their sidewall spacers, and forming a silicide layer on the first and second gate electrodes and on the semiconductor substrate where the first and second conductive type impurity regions are.

Method of fabricating cmosfet

DRAM matrix of basic organizational units each with pair of capacitors

A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well, forming a field oxide in the overlapping portion of the first and second conductive wells forming a first gate over the first conductive well and a second gate over the second conductive well, masking the first conductive well and implanting second conductive impurities on the second conductive well and masking the second conductive well and implanting first conductive impurities on the first conductive well.

Method for fabricating a CMOS

A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

Manufacturing process for a DRAM with a buried region

A method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device is disclosed. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole on the portion where a contact is to be formed; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and may be selected from high melting point metals including Co, Ti, Ta, Ni, Mo, and Hf. The ions used are ions including H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions may spread on/in the grain boundaries, or that the positive ions may bond with dangling bonds. Further, a silicidation heat treatment is carried out so that the silicide would be formed on the portion where the metal and the silicon substrate contact together. These heat treatments may be carried out simultaneously. The heat treatment for the spreading of the positive ions is carried out at a low temperature of about 300.degree.-500.degree. C., while the heat treatment of the silicidation reaction is carried out at a proper temperature depending on the metal used.

Process for formation of contact conductive layer in a semiconductor

Method for manufacturing DRAM device using high dielectric constant

A method for forming a via contact of a semiconductor device includes the steps of forming a first insulating layer on a substrate, forming a lower conducting layer on the first insulating layer, forming a third insulating layer on the lower conducting layer, forming a first photoresist on the third insulating layer, etching the third insulating layer to form a via pillar, removing the first photoresist, forming a second photoresist on the via pillar and the lower conducting layer, etching the second photoresist except on the via pillar and a portion of the lower conducting layer, forming a metal line by removing portions of the lower conducting layer from which the second photoresist has been etched, removing the second photoresist that has not been etched, forming a second insulating layer on the metal line, the first insulating layer, and the via pillar, etching the second insulating layer to expose an upper surface of the via pillar, etching the via pillar to thereby form a via hole through the second insulating layer, and forming an upper conducting layer on the second insulating layer, through the via hole, and in contact with the lower conducting layer.

Method for forming a via contact of a semiconductor device

DRAM having a buried region contacted through a field region

A method of forming a semiconductor device by concurrently forming both single-trenched small field regions and double-trench-extension large field regions, and the device so formed. The method includes: forming an insulating layer on a substrate; forming a mask layer on the insulating layer to cover only active regions such that small field regions and large field regions are left uncovered by the mask layer; increasing a thickness of the insulating layer in each field region in proportion to the width of that field region; removing all of the insulating layer in the small field regions while removing only some of the insulating layer in the large field regions so that, in width cross-section, the large field regions have an exposed substrate narrow edge-area that borders both sides of a remaining portion of the insulating layer; forming trenches in the substrate corresponding in location to the exposed substrate areas such that an intermediate-width trench is created in each small field region and such that a wide trench, having two trench-deepening extensions, is created in each large field region; putting conductive material into the trenches such that the trench-deepening extensions are filled completely and the intermediate-width trenches are at least partially filled; and converting a portion of the conductive material into an insulating cap.

Isolation region structure of semiconductor device and method for making

A method for forming wells of a semiconductor device, being capable of removing the topology between n- and p-well regions. The method of the present invention provides a twin well structure wherein the n-well region has a higher level than the p-well region. This method includes the steps of sequentially forming a buffering film and an oxidizable film over a semiconductor substrate, forming an anti-oxidation film over the oxidizable film, removing a portion of the anti-oxidation film disposed at a first well region of the semiconductor substrate, implanting impurity ions in the first well region of the semiconductor substrate and annealing the resulting structure, thereby forming a first well in the substrate, removing the anti-oxide film and the oxidizable film both disposed at a second well region of the substrate, and implanting impurity ions in the second well region of the semiconductor substrate and annealing the resulting structure, thereby forming a second well in the substrate.

Growing community of inventors

Chungcheongbuk-do, South Korea

Chang Jae Lee