Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Hyundai Electronics Ind. Co., Ltd.

Chang-Jae Lee

Nae-Hak Park

Jong-Kwan Kim

Won-Suck Yang

Jae-Il Ju

Jong Kwan Kim

Hyunsang Hwang

Hyeung-Tae Kim

Jun-Ki Kim

Tae Gak Kim

Jae-Jeong Kim

Chang-Reol Kim

Hyuk-Jin Kwon

Young-Jin Song

Hee-Sik Yang

Won-Hyuk Lee

Woun-Suk Yang

Gum-Jin Park

Hwan Myeong Kim

A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process. Also, by providing a conductive layer between the first and second gates, which electrically connects those gates, mutual diffusion of the impurities doping the polysilicon layers is prevented.

Method of fabricating semiconductor device

The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.

Device isolation structure and device isolation method for a semiconductor power integrated circuit

A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Fabrication method of semiconductor device with diagonal capacitor bit line

A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Memory cell structure for semiconductor memory device

A method of fabricating a semiconductor device having a memory device region and a logic device region on a substrate includes the steps of forming first and second gate lines on the substrate at the memory device region and the logic device region, respectively, forming a sidewall insulating layer on both sides of each of the first and second gate lines, forming a plurality of impurity regions in the substrate, forming a silicon nitride layer on the memory device including the first gate lines, forming a silicide layer on the second gate line and impurity regions at the logic device region, and forming an oxide layer on an exposed surface excluding portions over each one of the impurity regions at the memory region and the logic device region, respectively.

The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.

A fabrication method for a semiconductor memory device, which forms a capacitor over a bit line, includes the steps of forming an active region pattern on a semiconductor substrate, forming a field oxide region for electrically isolating single devices in the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film to serve as a gate electrode on the gate insulating film, forming a first insulating film having a first etching characteristic on the first conductive film, and patterning the first insulating film and the first conductive film to form a plurality of word line patterns. Next a second insulating film, having the first etching characteristic, is formed over the semiconductor substrate, and is etched to form sidewall spacers at lateral walls of each word line pattern. A third insulating film is then formed over the semiconductor substrate, and removed from regions where a bit line is to be formed. This exposes the active region and forms a bit line trench pattern. A bit line is then formed with portions thereof disposed in the bit line trench pattern, and a capacitor is formed over the bit line. The different etching characteristics of the insulating films allows for a larger contact hole to be formed thereby improving the contact hole aspect ratio.

Fabrication method for semiconductor memory device

Semiconductor device with diagonal capacitor bit line and fabrication

A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

Method for forming a semiconductor device incorporating a dummy gate

A metal wiring for semiconductor devices having a double-layer passivation film structure consisting of an intermetallic compound layer formed on a copper thin film and made of a metal reacting with copper to form an intermetallic compound and a metal nitride layer formed over the intermetallic compound. This double-layer passivation film structure is obtained by depositing a metal layer, capable of reacting with copper to form an intermetallic compound, over the copper wiring, and annealing the metal layer in a nitrogen atmosphere, thereby forming an intermetallic compound layer over the copper wiring. By virtue of the double-layer passivation film structure, the copper wiring has a great improvement in the reliability. A metal silicide layer is formed between a diffusion region and a diffusion barrier layer in the contact hole of the semiconductor device. The diffusion barrier layer, which is formed on an insulating layer doped with nitrogen ions, is changed into a metal nitride film. Accordingly, a reduced ohmic contact resistance and an improved passivation reliability are achieved.

Wiring structure for semiconductor device and fabrication method therefor

Memory cell structure for semiconductor memory device and fabricating

The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Process for making a semiconductor MOS transistor

A semiconductor fabrication apparatus which includes a collimator made of a net type heating material which generates Joule heating when electric power is supplied thereto. The apparatus includes a negative electrode having a metallic target, a positive electrode arranged opposite the negative electrode, on which positive electrode a semiconductor substrate is mounted, and the collimator being mounted between the negative electrode and the positive electrode and near the semiconductor substrate, with the collimator being made of a net type heating material and designed so that Joule heating is generated therein when a current is applied thereto.

Semiconductor fabrication apparatus having improved sputtering

An improved device isolation method for a semiconductor device capable of independently and compatibly providing an isolation film in the interior of well and an isolation film between wells during a consistent process, so that latch-up characteristic can be improved even in a device requiring a design rule of below 0.5 .mu.m, which includes a first step which combines a second step which forms a device isolation film within a well and a third step which forms a device isolation film between wells, the second and third steps being compatible to each other during the same step.

Growing community of inventors

Chungcheongbuk-do, South Korea

Chang-Jae Lee