Lg Display Co., Ltd.

Chang-Il Ryoo

Hyun-Sik Seo

Jong-Uk Bae

Yong-Yub Kim

A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the array substrate includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other; source and drain electrodes formed on the etch prevention layer; a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and a pixel electrode formed on the passivation layer and through the contact hole.

Array substrate and method of fabricating the same

An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.

Array substrate for display device and method of fabricating the same

A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the method includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer and an etch prevention layer on the gate insulating layer using a single mask, forming source and drain electrodes on the etch prevention layer, and forming a passivation layer including a contact hole on the source and drain electrodes and on the gate insulating layer, and forming a pixel electrode on the passivation layer and through the contact hole.

An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern. Further, the exposed portion of the auxiliary pattern exposes a channel region and including a metal oxide over the channel region. Also included is a data line over the gate insulating layer, the data line crossing the gate line to define the pixel region and being connected to the source electrode, a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode, and a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.

Growing community of inventors

Paju-si, South Korea

Chang-Il Ryoo