Samsung Electronics Co., Ltd.

Korea Institute of Science and Technology

Chang-hyun Cho

Ki-Nam Kim

Jae-Goo Lee

Tae-Young Chung

Gwan-Hyeob Koh

Ki-nam Kim

Jae-young Lee

Min-hee Cho

Won-Suk Yang

Won-suk Yang

Hong-Sik Jeong

Sang-hyeon Lee

Yong-Seok Ahn

Sung-Jin Kim

Sang-sup Jeong

Sung-Chul Kang

Chang-Jin Kang

Dae-Won Ha

Gyo-young Jin

Yong-chul Oh

Kyu-Hyun Lee

Soo-ho Shin

Kyu-pil Lee

Chul Ho Jung

Munsang Kim

Ju-Wan Kim

Heon-Cheol Kim

Byung-Keun Hwang

Mi-hyang Lee

Heon-cheol Kim

Chan-Ouk Jung

Mun-Sang Kim

Ho-Ryong Kim

Sang-Hyeon Baeg

Cheon-bae Kim

Jue-Goo Lee

Sang-Sup Jeong

Ho-royng Kim

Sang-hyeon Baeg

Kuk-han Yoon

Jong-ryul Jun

Hyun-Oh Shin

Jea-Sun Kim

Yo-Ha Hwang

A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Semiconductor device having capacitors

A harmonic drive according to the present invention comprises a plurality of internal gears; a band type of flexible gear provided with teeth engaged with each of the internal gears on its outer circumferential surface, the flexible gear having a pitch circumference length shorter than that of said internal gears; and a wave generating part disposed on an inner side of said flexible gear, the wave generating part generating a plurality of harmonic motions by deforming said flexible gear as the wave generating part rotates. Further, said flexible gear is formed integrally to engage with said plurality of internal gears so that the plurality of harmonic motions are overlapped, and one or more of said plurality of internal gears and said flexible gear are formed of profile shifted gears.

Harmonic drive using profile shifted gear

An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region

A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

Semiconductor memory device including storage nodes and resistors and method of manufacturing the same

A working robot, which is able to perform a required operation by locating a tool on a working position of a moving object, comprises a robot body moving with the object according to the movement of the object with more than one degree of freedom; an actuator mounted on a free end of the robot body and including a tool mounting unit, on which the tool is mounted, connected by a passive joint which reacts passively to small displacement of the object for locating the tool on the working position; and a control device for controlling the robot body, the actuator, and the tool.

Working robot, actuator and control method thereof

Methods of forming an integrated circuit device may include forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate. A gate insulating layer can be formed on the semiconductor substrate extending between the first and second spaced apart souce/drain regions. The gate insulating layer can have a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions. A thickness of the gate insulating layer can increase as it extends toward each of the source/drain regions. A gate electrode can be formed on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode. Related devices are also discussed.

Methods providing oxide layers having reduced thicknesses at central portions thereof

A method for arranging a power supply line in a semiconductor device including a plurality of memory cell array blocks and a semiconductor device are provided in order to supply stable operating voltages, such as a power supply voltage and a ground voltage, to a sense amplifier allocated to each of the plurality of memory cell array blocks. The method includes the steps of arranging a plurality of first interconnections that extend in one direction and are spaced apart from one another on a semiconductor substrate on which the plurality of memory cell array blocks are formed, forming a first insulating layer on the plurality of first interconnections, arranging a plurality of power reinforcing lines that extends in one direction and are spaced apart from one another on the plurality of first interconnections on the first insulating layer, forming a second insulating layer on the plurality of power reinforcing lines, and arranging a plurality of second interconnections that intersect the plurality of first interconnections and the plurality of power reinforcing lines on the second insulating layer. The plurality of second interconnections include a first group and a second group, and the second interconnections in the second group are electrically connected to the plurality of power reinforcing lines on the plurality of memory cell array blocks via contact plugs formed in the second insulating layer.

Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line

Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

Devices with active areas having increased ion concentrations adjacent to isolation structures

A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

Method of fabricating MOS transistors

Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.

Methods of forming spin on glass layers by curing remaining portions thereof

Methods of implanting ions into different active areas to provide active areas having increased ion concentrations adjacent to isolation structures

Self aligned contact pads in a semicondductor device and a method for forming thereof within etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

Methods of forming self-aligned contact pads on electrically conductive lines

A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Method for forming a dielectric layer

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Seoul, South Korea

Chang-hyun Cho