Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Chang-Hyuk Lee

Ho-Youb Cho

Jae-Kyung Wee

Jin-Keun Oh

Phil-Jung Kim

Hi-Hyun Han

Ju-Young Seo

Young-Ho Seol

Byoung-Jin Choi

Jae-Seok Park

Oh-Won Kwon

A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Semiconductor memory device for driving a word line

A semiconductor memory device stably performs a write operation with reduced current consumption. The semiconductor memory device includes a global data, a control unit, a termination resistor unit, and a storage unit. The global data line transmits data. The control unit generates a global control signal during a read operation or a write operation. The termination resistance unit supplies termination resistance to the global data line in response to the global control signal. The storage unit stores the data transmitted to the global data line while the termination resistance unit is inactivated. A method for driving the semiconductor memory device includes detecting a read operation or a write operation and supplying termination resistance when the read or write operation is detected.

Semiconductor memory device and method for driving the same

A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal.

Semiconductor memory device

A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.

Memory cell test circuit for use in semiconductor memory device and its method

A redundant circuit includes a plurality of bit line sense amp arrays including different local data buses, sharing one bit line sense amp, and being formed adjacently to each other, an input/output fuse unit for outputting a selection signal with different logic state depending on whether or not a first fuse is cut upon activation of a row active operation control signal, a fuse set for providing a redundant signal with different logic state based on whether or not a second fuse is cut and repair addresses upon activation of the row active operation control signal, and a redundant controller for logically operating the selection signal, the redundant signal and a strobe signal to thereby generate a bus control signal to selectively connect the bit line sense amp to the different local data buses.

Redundant circuit for semiconductor memory device

A semiconductor memory device for reducing data line length includes a plurality of data input strobe signal generation units each of which for generating a plurality of data input strobe signals based on a plurality of data input control code signals; and a plurality of data coders one-to-one corresponded to the plurality of data input strobe signal generation units for outputting data to a plurality of global input/output lines according to the plurality of data input strobe signals.

Semiconductor memory device with simplified data control signals

The present invention provides a semiconductor memory device for reducing a power consumption and securing an enough valid data window. A semiconductor memory device includes an align control signal generation unit for generating a plurality of align control signals sequentially activated by dividing a data strobe signal only when a data input/output is performed; and a data align unit for outputting a plurality of data which are sequentially inputted as a plurality of align data at the same time in response to the plurality of align control signals.

The present invention provides a semiconductor memory device for reducing a power consumption. A semiconductor memory device includes a command decoding unit for decoding a plurality of commands; a driving signal generation unit for generating a plurality of driving signals synchronized with Nth clocks of an internal clock from an activation timing of a CAS signal generated by the command decoding unit, wherein N is an even integer number; an address delay unit for receiving an internal address in response to the CAS signal and for delaying the internal address signal by synchronizing the internal address with the plurality of driving signals; and a data access block for performing a data access in response to the delayed internal address.

Disclosed herein is a semiconductor memory device for reducing an unnecessary current consumption occurred in an idle state or an active state. The semiconductor memory device includes a driving clock supply unit for supplying a driving clock during a read or a write operation of each bank; a delay unit for generating a read address or a write address in synchronization with the driving clock by delaying an address by a predetermined time based on one of an additive latency, a CAS latency and a combination thereof; and an output unit for latching the read address or the write address to output the latched signal as an internal column address.

There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a second address information signal to directly output or inversely output the received signal as a third address information signal in response to a first address information signal; a pipe output control unit for generating a plurality of pipe output control signals; a plurality of pipe latch units for storing a global data in response to a pipe input control signal and aligning the stored data in response to the first to the third address information signals, thereby outputting the aligned data synchronized by the pipe output control signals; and a data driving unit for outputting the aligned data as an external data in response to a first and a second DLL output clock.

Data output device of semiconductor memory device

A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Memory repair circuit using antifuse of MOS structure

A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Repair circuit using antifuse

An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation. For the purpose, the antifuse circuit includes a power-up detecting circuit for generating a power stabilization signal by detecting a supply voltage; a power-up pulse circuit for generating a first and a second control signal in response to the power stabilization signal; an antifuse programming circuit for, under the control of the first and the second control signals, detecting whether an antifuse element is programmed or not, latching the result of the detection and programming the antifuse element in response to an external high voltage and a precharge signal; a pin for receiving the external high voltage so as to program the antifuse element; a pad for providing the external high voltage to the inside of the chip; and a diode for supplying the external high voltage to the antifuse programming circuit and preventing a voltage of the antifuse programming circuit from being provided to the pin.

Growing community of inventors

Kyoungki-do, South Korea

Chang-Hyuk Lee