Winbond Electronics Corporation

Asia Optical Co., Ltd.

Chang-Hung Lin

Tzu-Ming Ou Yang

Feng-Jung Chang

Ming-Chyi Yang

A semiconductor structure including a substrate and a monitoring mark is provided. The substrate includes a monitoring region. The monitoring mark is located in the monitoring region. The top-view pattern of the monitoring mark includes a curved line and a recess. The curved line and the recess are opposite to each other, the curved line has a vertex, and the recess has a right-angled corner.

Semiconductor structure and manufacturing method thereof

Provided is a DRAM including: a substrate, a plurality of chop structures, and a plurality of buried word lines. The plurality of chop structures are located in the substrate. Each of the plurality of chop structures comprises a first portion and a second portion. The first portion is located above the second portion, and a width of the second portion is less than a width of the first portion. The plurality of buried word lines, located at bottoms of a plurality of buried word line trenches. The plurality of buried word line trenches passes through the first portion of the plurality of chop structures and the substrate.

Dynamic random access memory having word line buried in chop structure with different widths

A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.

Semiconductor structure and method for forming the same

A semiconductor structure includes a semiconductor substrate and a gate structure embedded in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer disposed over the gate electrode layer, and a semiconductor layer disposed over the barrier layer. The semiconductor structure also includes an air gap in the semiconductor substrate and exposing the barrier layer and the semiconductor layer.

Semiconductor structure with air gaps for buried semiconductor gate and method for forming the same

Provided are a semiconductor memory device with guard pillars and a manufacturing method thereof. The semiconductor memory device includes a substrate having a memory region and a periphery region surrounding the memory region, a plurality of bit line structures, a plurality of contacts, a plurality of guard pillars and a plurality of capacitors. The bit line structures are arranged parallel to each other on the substrate in the memory region. The contacts are disposed between the adjacent bit line structures and electrically connected to the substrate. The guard pillars are disposed on the substrate and located between the adjacent bit line structures at the boundary between the memory region and the periphery region. The capacitors are disposed on the plurality of contacts to be electrically connected to the plurality of contacts.

Semiconductor memory device with guard pillar and manufacturing method thereof

A buried word line structure, including a first isolation structure, a buried word line, a first barrier layer, a second barrier layer, a channel layer, and a second isolation structure, is provided. The first isolation structure is disposed in the substrate and has a trench. The buried word line is disposed on a bottom surface of the trench. The first barrier layer is disposed between the buried word line and a sidewall and the bottom surface of the trench. The second barrier layer covers a top surface of the buried word line and includes a main portion and an extension portion. The main portion is located on the buried word line, and the extension portion extends upward from periphery of the main portion. The channel layer is disposed on the first barrier layer and the second barrier layer. The second isolation structure is disposed on the channel layer.

Buried word line structure and manufacturing method thereof

Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.

Dynamic random access memory and method of manufacturing the same

A zoom lens includes a cam roll, straight-forward units, lens groups, a driving unit, a detecting unit and a micro-processing unit. The lens groups moved by the cam roll sequentially varies from a receiving status to a zeroing status, a macro shooting-distance status and a wide shooting-distance status. A datum point of the cam roll corresponds to the zeroing status of the lens groups. The detecting unit includes an impeller, a detecting portion and a photonic sensor. When the photonic sensor detects the datum point of the cam roll, the micro-processing unit determines the position of the datum point of the cam roll and to reset the rotation count of the impeller. When the photonic sensor detects a skew point of the cam roll, the micro-processing unit determines and amends the rotation count of the impeller to be equal to a predetermined value.

Growing community of inventors

Taichung, Taiwan

Chang-Hung Lin