Unity Semiconductor Corporation

Sandisk Technologies Inc.

Micron Technology Incorporated

Sandisk 3D LLC

Chang Hua Siau

Christophe J Chevallier

Seow Fong Lim

Darrell Rinerson

Bruce Lynn Bateman

Sri Rama Namala

Tianhong Yan

Yingchang Chen

Gopinath Balakrishnan

Grishma Shah

Qui V Nguyen

Kapil Verma

Xiaowei Jiang

Yingda Dong

George Matamis

Shigekazu Yamada

Hao Nguyen

Tz-Yi Liu

Kenneth Louie

Jeffrey Koon Yee Lee

Anurag Nigam

Kalyan Chakravarthy C Kavalipurapu

Sheng-Huang Lee

Kristopher Kopel

Kalyan Chakravarthy Kavalipurapu

Lu Tong

Roy E Scheuerlein

Jonathan Scott Parry

Robert W Ellis

Michele Piccardi

Koichi Kawai

Aaron Keith Olbrich

Walter Di Francesco

Jack Frayer

Takehiro Hasegawa

Siu Lung Chan

Kirubakaran Periyannan

Ali K Al-Shamma

Farookh Moogat

Khanh Vinh Nguyen

David A Eggleston

Vidyabhushan Mohan

Ashish Ghai

Lakshmi Kalpana Vakati

Wanfang Tsai

Luca Nubile

Yosuke Kato

Raj K Bansal

Ekamdeep Singh

Thomas Yan

Jeffrey Lee

Shingo Zaitsu

Naresh Battula

Yankang He

One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

Flash memory devices including dram

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods

A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

Memory device with multiple input/output interfaces

A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.

Microelectronic devices including staircase structures, and related memory devices and electronic systems

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Salvaging bad blocks in a memory device

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Memory cell sensing

A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.

Asymmetric plane driver circuits in a multi-plane memory device

A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Distributed compaction of logical states to reduce program time

Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

Memory cell programming including applying programming pulses of different pulse widths to different access lines

Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Growing community of inventors

Saratoga, CA, United States of America

Chang Hua Siau