Juniper Networks, Inc.

Chang-Hong Wu

Pradeep S Sindhu

David James Ofelt

Jean-Marc Frailong

Srihari Raju Vegesna

Sarin Thomas

Dennis C Ferguson

Hann-Hwan Ju

Stefan Alexander Dyckerhoff

Ashok Krishnamurthi

Pankaj Patel

Ramalingam Krishnamurthi Anand

Philip A Thomas

David P Chengson

Chi-Chung Kenny Chen

Gary S Goldman

Paul Kim

Devereaux C Chen

Ross Heitkamp

Aibing Zhou

John Delmar Johnson

Thomas Michael Skibo

Ramesh Padmanabhan

In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.

Deadlock-resistant fabric tree replication in a network device

In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

Digital bit insertion for clock recovery

In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.

Methods and apparatus for transmission of groups of cells via a switch fabric

A network device operating in operating in a Priority Flow Control (PFC) mode receives a stream of packets for outputting on a particular port, assigns each packet in the stream of packets to one of multiple buffer queues associated with the port, and generates, based on the assigning, packet counts for the multiple buffer queues. The network device aggregates the packet counts for a group of particular buffer queues, of the multiple buffer queues, that are not subject to a PFC restriction, to create an unrestricted aggregated count. The network device determines whether the unrestricted aggregated count exceeds a flow-control threshold for the group of particular buffer queues and sends, to an upstream queue scheduler, a flow control signal when the unrestricted aggregated count exceeds a flow-control threshold.

Transmit-buffer management for priority-based flow control

A network device receives traffic associated with a network of intermediate network devices and user devices, classifies the received traffic, and allocates the classified traffic to traffic queues. The network device also schedules particular queued traffic, provided in the traffic queues and bound for particular intermediate network devices, using a hybrid weighted round robin (WRR) scheduler where the hybrid WRR scheduler schedules the particular queued traffic according to one of a 1-level WRR schedule, a 1.5 level WRR schedule, or a 2-level WRR schedule. The network device further provides the particular queued traffic to the particular intermediate network devices based on the scheduling of the hybrid WRR scheduler.

Hybrid weighted round robin (WRR) traffic scheduling

A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Low latency serial memory interface

A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information.

Preserving the order of packets through a device

Systems and methods for allocating bandwidth for processing of packets

A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.

Single cycle cyclic redundancy checker/generator

A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal

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Saratoga, CA, United States of America

Chang-Hong Wu