Samsung Electronics Co., Ltd.

Chang-ho Shin

Dong-soo Lee

Sun Chul Kim

Seog-Ho Lim

Jae-jun Bang

Jong-Hyun Choi

Yong-jae Lee

Young-Hun Seo

Nam-Jong Kim

Young-Sun Min

Seung-hyun Cho

Myoung-sun Ha

Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.

Memory devices including voltage generation circuit for performing background calibration

Provided are a light source module and a backlight unit (BLU) including the same. The light source module includes a substrate including a base plate extending in a first direction and a pair of dam structures stacked on opposing sides of the base plate along a second direction, orthogonal to the first direction, and extending along the base plate in the first direction, wherein the pair of dam structures are spaced apart from each other along a third direction, orthogonal to the first and second directions. A plurality of light-emitting devices are mounted on the substrate between the pair of dam structures and spaced apart from one another in the first direction. An encapsulation layer covers at least one side surface and a top surface of each of the plurality of light-emitting devices. A height of the pair of dam structures is greater than a height of the encapsulation layer.

Light source module, method of manufacturing the module, and backlight unit including the light source module

A light source module according to some example embodiments includes a first substrate and a plurality of second substrates. The first substrate includes a plurality of connectors configured to at least receive a supply of electrical power and a plurality of first connection pads that are configured to be electrically connected to the plurality of connectors. The second substrates each include a plurality of mounting elements on an upper surface and a plurality of second connection pads on a lower surface of the second substrate and configured to be electrically connected to the plurality of mounting elements. Each mounting element may be connected to a separate light-emitting device. A plurality of connection members may electrically connect the first connection pads of the first substrate to the plurality of second connection pads of the plurality of second substrates.

Light source module and backlight assembly having the same

A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter a deep-power-down (DPD) mode without generating the first initialization signal. The first initialization signal may be generated if the semiconductor memory device exits the DPD mode.

Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same

A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array internal voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit internal voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

Semiconductor memory device having a voltage boosting circuit

A semiconductor device has a power-saving mode and a normal mode. A voltage booster within the semiconductor device responds to the normal mode and the power-saving mode by controlling various internal operating voltages of the semiconductor device using a level shifter, an internal voltage booster, and a voltage boosting circuit. The initial voltage booster is configured to transmit an external power supply voltage through an initial boosting node to a voltage boosting terminal in response to the level shifter output signal during the normal mode, and to block transmission of the external power supply voltage to the initial boosting node to decrease a voltage level of the initial boosting node during the power-saving mode.

Voltage booster for semiconductor device and semiconductor memory device using same

In a power-on reset circuit and a method of generating a power-on reset signal tolerant of variation of an ambient temperature, the power-on reset circuit includes a first power-on reset unit, a second power-on reset unit and a logic gate. The first power-on reset unit generates a first power-on reset signal that is activated at a first level of a power supply voltage at a first temperature, and is activated at a second level of the power supply voltage at a second temperature. The second power-on reset unit generates a second power-on reset signal that is activated at the second level at the first temperature, and is activated at the first level at the second temperature. The logic gate executes a logical disjunction operation or a logical conjunction operation of the first power-on reset signal and the second power-on reset signal and generates a third power-on reset signal.

Circuit and method for power-on reset

A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

Growing community of inventors

Suwon-si, South Korea

Chang-ho Shin