Globalfoundries Inc.

Lam Research Corporation

Chang Ho Maeng

Haigou Huang

Taejoon Han

Hoong Shing Wong

Gabriel Padron Wells

Kristina Trevino

Ruilong Xie

Chanro Park

Haiting Wang

Andy C Wei

Laertis Economikos

Guillaume Bouche

Jinping Liu

Huang Liu

Xintuo Dai

Huy Cao

Bharat V Krishnan

Gowri Kamarthy

Dae Geun Yang

Songkram Srivathanakul

Haifeng Sheng

Dae-han Choi

Pei Liu

Ganesh Upadhyaya

Wontae Hwang

Ashish Kumar Jha

Xing Zhang

Junsic Hong

Xiaofeng Qiu

Kenneth Andrew Bates

Shyam Pal

Tae Hoon Lee

Tae-Hoon Kim

Yuan-Hung Liu

Isabelle Orain

Yuan-Hung Lin

Anthony Ozzello

Ja-Hyung Han

SangWoo Lim

Shivaji Peddeti

The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.

Embedded silicon carbide block patterning

A starting semiconductor structure includes a layer of filler material, a hard mask layer over the layer of filler material, and filler material lines over the hard mask layer. The starting semiconductor structure is placed in an etching chamber, and oxygen gas and high plasma power are inserted into the etching chamber and oxidizing, resulting in one or more of the filler material lines being oxidized, the filler material line(s) increasing in width from oxidizing, and etching the hard mask layer with a chemistry that is non-selective to the oxidized filler material lines and hard mask layer, and which has a stronger lateral etch selectivity to the oxidized filler material lines than the hard mask layer.

Oxidizing filler material lines to increase width of hard mask lines

Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Semiconductor structures with coplanar recessed gate layers and fabrication methods

Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.

Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same

Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Reducing gate height variance during semiconductor device formation

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Clifton Park, NY, United States of America

Chang Ho Maeng