Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Chang-Ho Do

Jae-Il Kim

Jae-Hyuk Im

Hwang Hur

Jin-Il Chung

Jae-Jin Lee

Jae-Bum Ko

Yong-Ki Kim

Yeon-Woo Kim

Tae-Hyung Jung

Bok-Moon Kang

Dong-Keun Kim

Ki-Ho Kim

Jee-Yul Kim

Jung-Won Suh

Jae-II Kim

Jin-Seok Son

Soo-Man Hwang

Dong-Geun Lee

A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.

Semiconductor memory device

An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.

Integrated circuit chip and semiconductor memory device

A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.

Semiconductor memory device and method for generating bit line equalizing signal

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Semiconductor memory device, test circuit, and test operation method thereof

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

A semiconductor memory device includes a main word line signal generator configured to generate a main word line signal having a first swing width, a sub-word line signal generator configured to generate a first sub-word line signal and a second sub-word line signal having a second swing width and a third swing width, respectively, a first sub-word line driver configured to drive a corresponding sub-word line with the first sub-word line signal or a negative word line voltage in response to the main word line signal, and a second sub-word line driver configured to drive the corresponding sub-word line with the negative word line voltage in response to the second sub-word line signal.

A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.

Multi-port memory device with serial input/output interface

An internal signal monitoring device in a semiconductor memory device includes: an internal signal input unit to receive an internal signal to be monitored and having an output to provide a monitor source signal in response to a test mode signal; and an internal signal output unit having an input coupled to the output of the internal signal input unit, the internal signal output unit to transmit the monitor source signal to a predetermined pad of the semiconductor memory device in response to the test mode signal.

Internal signal monitoring device in semiconductor memory device and method for monitoring the same

An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.

Internal negative voltage generation device

A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode.

Semiconductor memory device for increasing test efficiency by reducing the number of data pins used for a test

A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

Apparatus and method for transmitting/receiving signals at high speed

An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Internal voltage generating circuit of semiconductor device

A semiconductor device includes a pads for receiving a reference voltage and input signals from an external device, a unit gain buffer for receiving the reference voltage as an input, input buffers for identifying a corresponding one of the input signals based on an internal reference voltage outputted from the unit gain buffer, external electrostatic discharge protectors connected to a transmission path of the reference voltage and transmission paths of input signals, and internal electrostatic discharge protectors connected to the transmission path of the reference voltage and the transmission paths of the input signals.

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Kyoungki-do, South Korea

Chang-Ho Do