Samsung Electronics Co., Ltd.

Chang-ho An

Sung-ho Lee

Ki-won Seo

Min-Sung Kim

Junho Song

Jae-Wook Kwon

Jae-wook Kwon

Chul-Ho Choi

Mi-Ran Kim

A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.

Multi-channel semiconductor device and display device comprising same

An output buffer having a high slew rate, a method of controlling the output buffer, and a display driving device including the output buffer. The output buffer includes: a first output buffer adapted to output a source line driving signal to a first output terminal in response to a first control signal and output a source driving signal to a second output terminal in response to a second control signal; a second output buffer adapted to output a source line driving signal to a third output terminal in response to the first control signal and output a source line driving signal to a fourth output terminal in response to the second control signal; and a feedback circuit for connecting the first through fourth output terminals to negative input terminals of the first and second output buffers in response to the first control signal and the second control signal.

Output buffer having high slew rate, method of controlling output buffer, and display driving device including output buffer

A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

Buffer amplifier with minimized power consumption and display driver including the same

A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.

Delay-locked loop circuit and semiconductor device including the same

A source driver employed in a liquid crystal display device uses a slew-rate control signal to regulate a slew rate of its output buffers, which makes an output voltage selectively operable at a low slew rate. Such a source driver can reduce (if not prevent) distortion of a common voltage.

Growing community of inventors

Hwaseong-si, South Korea

Chang-ho An