Samsung Electronics Co., Ltd.

Chang-gyu Kim

Ji-hyun Choi

Seok-ji Hong

Min-su Baek

Jae-deok Kim

Seok-Ji Hong

Woo-in Chung

A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Method for planarizing a semiconductor substrate

A method is disclosed for manufacturing a semiconductor device that is capable of minimizing a step difference between DRAM and logic regions of a semiconductor substrate by forming a capacitor in the DRAM cell region and then forming a metal interconnection in the logic region after deposition of a first insulating layer before planarization, the metal interconnection having height similar to the capacitor. Although a second insulating layer is deposited over the substrate, a step between the DRAM cell region and local region can be minimized because of the metal interconnection formed in the logic region. Thus, although only either CMP or etch back process is used, planarization of the second insulating layer is allowed.

Method for manufacturing semiconductor device capable of improving

Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g., SiO.sub.2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self-aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask. Then, the mask and second portions of the electrically insulating layer extending opposite the mask, are etched in sequence to define an electrically insulating region in the trench. This latter etching step is preferably not performed using a chemical mechanical polishing step to limit the likelihood of isolation deterioration caused by the dishing phenomenon.

Methods of forming shallow trench isolation regions using plasma

Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.

Trench isolation methods including plasma chemical vapor deposition and

An isolation region is formed on a substrate by forming spaced apart mesas on the substrate, each mesa including a barrier region which caps the mesa. An insulation riser is then formed in the substrate, disposed between and separated from the spaced apart mesas. Spaced apart trenches are formed in the substrate on opposite sides of the insulation riser, each trench disposed between the insulation riser and a respective one of the mesas. An insulating material layer is formed on the substrate, the insulating material layer filling the spaced apart trenches and covering the insulation riser and the mesas, and then is chemical mechanical polished to expose the mesas and thereby form an isolation region spanning the spaced apart trenches. Preferably, barrier spacers are formed on sidewall portions of the mesas, and a surface portion of the substrate between the barrier regions is thermally oxidized using the barrier regions and the barrier spacers as an oxidation barrier to form the insulation riser. The isolation region includes an insulation riser at the surface of the substrate, extending from the surface into the substrate, and an insulation region on the substrate, covering the insulation riser and extending into the spaced apart trenches. The insulation region may include insulation spacers adjacent sidewall portions of the spaced apart trenches, and an insulation region on the substrate, covering the insulation riser and extending into the spaced apart trenches to contact the insulation spacers.

Methods of fabricating trench isolation regions with risers

A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a semiconductor substrate, exposing a portion of the semiconductor substrate in which a device isolation region is to be formed by selectively etching the first and second material layers, forming side wall spacers on exposed lateral sidewalls of the first and second material layers, forming a trench by etching the exposed portion of the semiconductor substrate using the side wall spacers as a mask, depositing an insulating film having an underlayer dependency characteristic over the surface of the resulting structure, etching the surface of the insulating film, and removing the first and second material layers.

Growing community of inventors

Kyungki-do, South Korea

Chang-gyu Kim