Mediatek Corporation

Silicon Integrated Systems Corporation

Chang-Fu Lin

Cheng-Che Chen

Shu-Wen Teng

Wei Cheng Gu

Wen-Hsiang Lin

Yen-Yu Lin

Jen-Pin Su

Tsan-Hui Chen

Chun-Chieh Wu

Chih-Wei Ko

Ting-Cheng Hsu

Ching-Chao Yang

Wei-Cheng Gu

Chih-Jou Lin

Shih Tang Lin

An electronic device is disclosed. The electronic device comprises a transmitter, a converter, and a receiver. The transmitter transmits data and a control signal. The converter receives the control signal from the transmitter and converts the control signal. The receiver receives the data from the transmitter via a data bus isolated from the converter and receives the converted control signal from the converter. The data transmitted from the transmitter is directly electrically connected to the receiver.

Systems and methods for control signal and data transmission between various types of electronic modules

An apparatus for capturing and storing real-time images is provided. A camera module records frames corresponding to sensed light, outputs pixel data of the frames on a data bus, and generates synchronization control signals to control the synchronized transmission of the frames. An interrupt controller receives the synchronization control signals and correspondingly generates interrupt signals. A processing unit receives the interrupt signals, fetches the pixel data of the frames on the data bus according to at least one of the interrupt signals, and stores the fetched pixel data in a memory device.

Apparatuses for capturing and storing real-time images

The invention discloses a general purpose interface controller, including a slave interface controller and a master interface controller, used to exchange data among master devices and slave devices in an electronic device. The slave interface controller receives data and a first control signal from one of the master devices, and converts the first control signal to a request signal. The master interface controller receives the data and the request signal from the slave interface controller, converts the request signal to a second control signal recognized by at least one of the slave devices, and forwards the data and the second control signal to the slave device.

General purpose interface controller of resoure limited system

A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Processing modules with multilevel cache architecture

In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetching device is also disclosed.

Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems

In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetch device is also disclosed.

A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY&num; and TRDY&num; signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.

Method and apparatus for transmitting registered data onto a PCI bus

The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

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Hsinchu, Taiwan

Chang-Fu Lin