Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Chang-Fu Kuo

Beng Ong

Wee Liang Lien

Shou-Tsung Wang

Chi-Ming Hsiao

Min Jie Wu

Chao-Hsin Lu

Ling-Wei Ke

Po-Sen Tseng

Kuang-Chung Tao

Minjie Wu

Kuang-Kai Teng

Ling-Wei Ko

Jen-Chiou Bo

A wireless receiver with automatic gain control and a method for automatic gain control of a receiving circuit utilized in a wireless receiver are provided. The receiving circuit includes a programmable gain amplifier and a low noise amplifier, and the method includes: comparing a gain code of the programmable gain amplifier with a predetermined code range, wherein the gain code is determined by a frequency signal received through the low noise amplifier; and adjusting a gain of the low noise amplifier when the gain code is out of the predetermined code range.

Wireless receiver with automatic gain control and method for automatic gain control of receiving circuit utilized in wireless receiver

An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

Voltage controlled oscillator

A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

Mobile communication system with integrated GPS receiver

A system capable of limiting a current through a load and a method thereof. The system comprises a current sensor, a determination circuit, and a current mirror circuit. The current sensor, coupled to the load, produces a current indication indicating the current. The determination circuit, coupled to the current sensor, generates a short-circuit signal when the current exceeds a predetermined threshold. The current mirror circuit, coupled to a voltage source, the current sensor and the determination circuit, comprises a current mirror and a bypass path, delivers a mirrored current from the current mirror to the load upon receiving the short-circuit signal, and passes the current from the voltage source through the bypass path to the load in the absence of the short-circuit signal.

Current limiter system, circuit and method for limiting current

The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

Phase-locked loop with VCO tuning sensitivity compensation

A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

Phase lock loop applying in wireless communication system and method thereof

A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

Fast locking method and apparatus for frequency synthesis

A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

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Hsin-Chu, Taiwan

Chang-Fu Kuo