Other

Texas Instruments Corporation

Drs Technologies, Inc.

Raytheon Ti Systems, Inc.

Drs Sensors & Targeting Systems, Inc.

C.f. Wan Incorporated

Chang-Feng Wan

Richard Scott List

Dwight Urban Bartholomew

Curtis Gene Garrett

Pradip Mitra

John H Tregilgas

Joseph D Luttmer

Steven N Frank

Michael A Kinch

Frank C Sulzbach

Jeffrey Don Beck

Peter D Dreiske

Julie S England

Yingsheng Tung

David E Fleming

In the preferred embodiment of the present invention, narrow bandgap II-VI compound semiconductor HgCdTe (0.1&#x2266;x&#x2266;0.5) (HgCdTe) wafers are annealed under Cd supersaturated conditions by exposing the HgCdTe planar or mesa surfaces to a Cd molecular beam in a vacuum deposition system before, during, and/or after anneals performed during individual photodiode fabrication process steps or HgCdTe epitaxial growth steps for eliminating or neutralizing the bulk or interfacial defects.

Method of cadmium molecular beam based anneals for manufacture of HgCdTe photodiode arrays

An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.

Hermetic packaging and method of manufacture and use therefore

An avalanche photodiode is operated in avalanche mode at a selected reverse bias that achieves high gain and a reduced gain normalized dark current.

Method of operating an avalanche photodiode for reducing gain normalized dark current

A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.

The present invention is related to a method for manufacturing micro-electro-mechanical systems (MEMS) having movable and stationary suspended structures formed from mono-crystalline silicon wafer or chip, bonded to a substrate wafer with an polymer adhesive layer that serves as spacer and as a sacrificial layer which is undercut by dry etch means. The substrate wafer contains electronic circuits for sensing and actuating the suspended structure by electrical means. Electrical interconnections between the suspended structures and the substrate can be made by etching through via holes in the suspended structure and the adhesive, depositing metal layers in the via holes, and removing the metal layers from outside the via holes. The metal layers in the via holes can also be used as pillars for supporting the suspended structures. This method can be used to manufacture inertial sensors.

Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore

A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

System and method of fabricating micro cavities

An embodiment of the present invention provides a stepping actuator, comprising a suspended membrane comprising a plurality of movable electrodes connected by plurality of spring hinges to a payload platform; and anchors connecting said membrane to a substrate, said substrate comprising a plurality of fixed electrodes; wherein said movable electrodes of said suspended membrane and said fixed electrodes from said substrate form parallel-plate electrostatic sub-actuators.

Stepping actuator and method of manufacture therefore

A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

A micro-electro-mechanical device and method of manufacture therefore with a suspended structure formed from mono-crystalline silicon, bonded to a substrate wafer with an organic adhesive layer serving as support and spacer and the rest of the organic adhesive layer serving as a sacrificial layer, which is removed by a dry etch means. Said substrate wafer may contain integrated circuits for sensing and controlling the device.

This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

Thermoplastic mounting of a semiconductor die to a substrate having a

Micro-electro mechanical device made from mono-crystalline silicon and

This invention relates to a process and structure for performing a high temperature or other process on both sides of a thin slice of material or die prior to being placed onto a integrated circuit or multi-chip module. In a particular embodiment, a process and structure is given to provide for double sided interdiffusion for passivation of a Mercury Cadmium Telluride (MCT) film which is mounted to a read-out integrated circuit (ROIC) face side up in order to fabricate vertically integrated Focal Plane Arrays (FPAs) with reduced dark currents and improved performance. The process of the present invention also allows for the insertion of novel materials such as Double Layer Heterojunction (DLHJ), MBE, MOCVD, etc. in the vertical integrated approach to FPAs.

Double sided interdiffusion process and structure for a double layer

A hybrid focal plane array has p-n junction photodiodes formed in a substrate (10) of HgCdTe which is passivated by a cap layer (12) of Cd-rich CdTe. The active surface of the HgCdTe substrate is passivated by annealing at a temperature sufficient to support interdiffusion between the Cd-rich CdTe capping layer (12) and the HgCdTe substrate (10). Use of the CdTe capping layer (12) with a slight excess Cd maintains the surface of the HgCdTe substrate (10) in a metal-rich phase condition.

Method using cadmium-rich CdTe for lowering the metal vacancy

Channel stops for MIS infrared photodetector devices in Hg.sub.1-x Cd.sub.x Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.

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Dallas, TX, United States of America

Chang-Feng Wan