Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang-Chih Huang

Kuo-Chyuan Tzeng

Yuan-Tai Tseng

Jui-Yu Pan

Fu-Ting Sung

Harry-Hak-Lay Chuang

Chung-Chiang Min

Tsung-Hsueh Yang

Yihuei Zhu

Tsung-Hao Yeh

Han-Yu Chen

Wan-Chen Chen

Kao-Chao Lin

Yi-Tzu Lin

A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.

Planarization-less phase change material switch

Various embodiments of the present application are directed towards an integrated chip including a first conductive interconnect structure overlying a substrate. A first memory stack is disposed on the first conductive interconnect structure. A second conductive interconnect structure overlies the first memory stack. The second conductive interconnect structure is spaced laterally between opposing sidewalls of the first conductive interconnect structure. A third conductive interconnect structure is disposed on the first conductive interconnect structure. A top surface of the third conductive interconnect structure is vertically above the second conductive interconnect structure.

Bit line and word line connection for memory array

A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.

Encapsulated phase change material switch and methods for forming the same

Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Layout for reducing loading at line sockets and/or for increasing overlay tolerance while cutting lines

Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer is disposed on the first electrode. A second electrode overlies the data storage layer. A buffer layer is disposed between the data storage layer and the second electrode.

Buffer layer in memory cell to prevent metal redeposition

An embodiment phase-change memory device includes a first electrode formed over an interconnect layer, a phase-change memory element formed over the first electrode, a second electrode formed over the phase-change memory element, and an oxygen-free spacer layer formed over sidewalls of the phase-change memory element. The phase-change memory element may include a germanium-antimony-tellurium alloy or an aluminum-antimony alloy. The phase-change memory device may include a carbon layer, configured as a heater element, formed between the first electrode and the phase-change memory element. The oxygen-free spacer layer may include SiN, SiC, or SiCN and may further include chlorine, fluorine, argon, chlorine and argon, fluorine and argon, or a mixture of chlorine, fluorine, and argon. The oxygen-free spacer layer may further include a composition that varies with position within the oxygen-free spacer layer. A further embodiment includes the phase-change memory device coupled to a selector element within a phase-change random-access memory structure.

In-situ formation of a spacer layer for protecting sidewalls of a phase change memory element and methods for forming the same

A phase change memory device includes a first electrode, a second electrode, a phase change region, a first spacer and a second spacer. The second electrode is disposed over the first electrode. The phase change region is disposed between the first and second electrodes. The first spacer laterally covers the phase change region. The second spacer laterally covers the first spacer, and has a thermal conductivity smaller than that of the first spacer.

Phase change memory device and method for manufacturing the same

Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.

Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

Memory arrays including continuous line-shaped random access memory strips and method forming same

Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

Growing community of inventors

Taichung, Taiwan

Chang-Chih Huang