Vintomie Networks B.v., LLC

Macronix International Co., Ltd.

Ruizhang Technology Limited Company

Controlnet, Inc.

Macronix America, Inc.

Chang-Chi Liu

Marwan M Hassoun

David Erich Tetzlaff

James Little

Steve Wang

Ming-Chang Su

Yu Liao

Michael A Smith

Jung-Yu Lee

Keith Wa Chau

Methods, apparatuses, and system for performing at least one of error correction or error detection are described. In one embodiment, a radio frequency identification (RFID) tag receives a signal activating or interrogating the tag. The tag includes memory that stores data associated with the tag. The tag performs at least one of error detection or error correction on the stored data. The error detection includes detecting, by the tag, that one or more bits of the stored data are inflicted with an error. The error correction includes correcting the erroneous bit if the error affects less than a predetermined number of the bits of the stored data. The tag transmits the stored data to a reader in response to the detection or correction. The reader can analyze the stored data for additional information about the error or provide the stored data to another computing system that performs the analysis.

Selective application of error detection and correction for radio frequency identification

Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.

Combined echo and crosstalk cancellation

An interface device allows communication between a 1394 device and an Ethernet via an 802.3 PHY. To the 1394 link, the device appears as a 1394 PHY, to the 802.3 PHY, the device appears as an 802.3 MAC. The interface device includes a 1394 PHY-link link interface, a Gigabyte Media Independent Interface (GMII), checksum padding and checksum stripping units, emulated 1394 PHY registers, and a clock generation unit. The interface device uses two clocks to supply timing clocks for the 1394 link and for the 802.3 PHY. For speed matching, the interface device matches the data rate of the link (S100, S200, S400, S800) with the PHY (nominally 1 Gbps) using a padding algorithm. The interface device provides the link with management information through a set of IEEE 1394 compatible registers that are accessed through the 1394 interface, emulating a single port 1394 PHY. The interface device also manages the IEEE 802.3 PHY as would a MAC through the MDC/MDIO interface.

Interface device for ethernet transceiver and 1394 controller

A device for coupling a first network medium to a second network medium. A first port is coupled to the first network medium and a second port coupled to the second network medium. A memory stores a first plurality of indications and a second plurality of indications. The indications in the first plurality of indications correspond to respective sets of addresses and indicate whether at least one address in the respective set of addresses may be accessible through the first network medium. The indications in the second plurality of indications correspond to respective sets of addresses and indicate whether at least one address in the respective set of addresses may accessible through the second network medium. A connecting circuit is coupled to the first port, the second port, and the memory. The connecting circuit causes the ports to pass or block a packet from the first network to the second network. The packet has a destination address. The connecting circuit causes the ports to pass or block based on a first indication from the first plurality of indications and a second indication from the second plurality of indications. The first indication corresponds to a set of addresses including the destination address of the packet. The second indication corresponds to the set of addresses including the destination address of the packet.

Bridge device with self learning between network media and integrated

A 100BASE-T compliant integrated circuit multiport repeater provides one or more medium independent interfaces (MII's) and a plurality of physical interfaces. This facilitates connection of the repeater to one or more external medium access controller devices also implementing the MII standard. The multiport repeater device shares status, configuration and control management function of the MII among the plurality of physical ports. Therefore, only one MII physical address is needed for each multiport repeater, rather than for each physical transceiver in the system. The medium independent interfaces on the repeater chip share a number of pins and logic so that the total number of I/O pins required for a repeater chip according to the present invention with multiple medium independent interfaces is substantially reduced over a similar device which might have a plurality of independent medium independent interfaces. The user of the repeater is capable of configuring the chip to handle a variety of different kinds of physical communication medium on a port by port basis, using the MII management bus.

Expandable integrated circuit multiport repeater controller with

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Fremont, CA, United States of America

Chang-Chi Liu