United Microelectronics Corp.

Chang-Chi Huang

Po-Chao Tsao

Ming-Tsung Chen

Yu-Lan Chang

Yi-Yiing Chiang

Chung-Ju Lee

Yi-Wei Chen

Feng-Yi Chang

Jiunn-Hsiung Liao

Cheng-Tung Huang

Kuan-Yang Liao

Pei-Yu Chou

Sheng-Hao Lin

Chao-Ching Hsieh

Ying-Chih Lin

Chih-Ning Wu

Tzung-Yu Hung

Chih-Wen Feng

Yi-Chung Sheng

Shih-Chieh Hsu

Tong-Hsin Lee

Shih-Chien Hsu

An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

Opening structure for semiconductor device

An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

Opening structure with sidewall of an opening covered with a dielectric thin film

A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.

Method of fabricating openings and contact holes

A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

Metal oxide semiconductor transistor

A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Fabricating method for a metal oxide semiconductor transistor

A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600&#xb0; C.

Method of fabricating nickel silicide

A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process to form a retarded interface layer between the silicon layer and the gate and source/drain region; forming a metal layer on the silicon layer; and reacting the metal layer with the silicon layer for forming a silicide layer.

Method of performing salicide processes on MOS transistors

A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600&#xb0; C.

Semiconductor device having nickel silicide and method of fabricating nickel silicide

A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench. A gate oxide is formed on the substrate with a thickness larger at the top edge corner of the trench than elsewhere.

Method of fabricating gate oxide

A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device. Since the offset spacers are formed on the sidewalls of the polysilicon lines before the photoresist layer is removed, the offset spacers can protect the polysilicon lines from being broken.

Growing community of inventors

Miao-Li Hsien, Taiwan

Chang-Chi Huang