Rdc Semiconductor Co., Ltd.

Chang-Cheng Yap

Bo-Yuan Shih

Ming-Chi Shih

A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.

Multi-core processor, controlling method thereof and computer system with such processor

A pulse processor includes a phase/pulse width sampler, a first calculator, a second calculator, a latching device, and a pulse width modulator. The phase/pulse width sampler generates an input direction signal, an input phase number and an input pulse width number according to a first signal and a second signal of the command pulse group. The first calculator is used for multiplying the input phase number by P/Q, thereby generating a target phase number, wherein P and Q are positive integers. The second calculator is used for multiplying the input pulse width number by Q/P, thereby generating a target pulse width number. The latching device receives the input direction signal and outputs a target direction signal. The pulse width modulator receives the target direction signal, the target phase number and the target pulse width number, and outputs a transferred pulse group.

Pulse processor of servo motor system

An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

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Hsinchu, Taiwan

Chang-Cheng Yap