Samsung Electronics Co., Ltd.

Chang-Bum Kim

Sung-Hoon Kim

Sunghoon Kim

Sung Hoon Kim

Daeseok Byeon

Dae Seok Byeon

Hyang-Ja Yang

Mun-Hyun Do

Duk-Min Kwon

Gyo-Soo Choo

Jin-Sung Yang

Yoon-Gun Jang

Woo-Joung Kim

A vertical memory device includes a gate line structure including a cell region in which a vertical channel structure is formed, and a first connection region and a second connection region which are respectively arranged at first and second ends of the cell region in a first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line which are parallel to a top surface of the substrate and arranged as steps in a second direction perpendicular to the first direction. The first protrusion of the second connection region is arranged diagonally from the first protrusion of the first connection region with respect to a center line of the cell region which is parallel to the first direction.

Vertical memory device

A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

Semiconductor wafer

An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

Integrated circuit and semiconductor device including same

A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.

Nonvolatile memory device including row decoder

A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.

Three dimensional semiconductor memory devices

An optical proximity correction (OPC) verifying method including checking a first location of a first pattern in a layout of a stacked memory device, calculating a shift value of the first pattern according to the first location, obtaining a difference value between the first location and a second location of a second pattern formed through an OPC with respect to the first pattern, and determining whether the OPC is to be performed again, based on the shift value and the difference value.

Stacked memory device, optical proximity correction (OPC) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device

A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

Memory device having cell over periphery structure and memory package including the same

In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response to a program command, a negative bias voltage is applied to the selected word line, a verification pass voltage is applied to an unselected word line after the negative bias voltage is applied to the selected word line, and a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, is applied to the selected word line.

Nonvolatile memory devices and methods of programming and reading nonvolatile memory devices

Disclosed is a multimode optical fiber having a structure to reduce scattering loss which includes a core divided into a central region having the optimal refractive index according to an optimal core shape index minimizing the scattering loss of the multimode optical fiber, and a peripheral region having the refractive index lower than that of the central region; and a cladding enclosing the core and having the refractive index lower than the lowest refractive index of the core.

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Seoul, South Korea

Chang-Bum Kim