Intel Corporation

International Business Machines Corporation

Chandrashekhar Ramaswamy

Sanka Ganesan

Henning Braunisch

Kemal Aygun

Eric C Palmer

Evan G Colgan

Mark D Summers

Charan K Gurumurthy

Herbert I Stoller

Mark S Hlad

George A Katopis

Thomas G Ruttan

A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Input/output package architectures

An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Substrate package with through holes for high speed I/O flex cable

Input/output package architectures, and methods of using same

In one embodiment, the present invention includes a circuit board having integrated contacts to mate with corresponding pads of a semiconductor device. At least some of the integrated contacts are of varying sizes to enable different contact resistances between the corresponding integrated contacts and pads, enabling reduced loading forces to adapt the semiconductor device to the circuit board. Other embodiments are described and claimed.

Providing variable sized contacts for coupling with a semiconductor device

A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned to insure that the chips requiring the lowest thermal resistance has the thinnest layer of a thermal adhesive or metal or solder interface between the chip and thermal spreader.

Multiple power density chip structure

Growing community of inventors

Chandler, AZ, United States of America

Chandrashekhar Ramaswamy