Taiwan Semiconductor Manufacturing Comp. Ltd.

Chandrashekhar Prakash Savant

Shahaji B More

Chia-Ming Tsai

Tien-Wei Yu

Chun Hsiung Tsai

Ming-Te Chen

Ke-Chih Liu

Kin Shun Chong

Yu-Ming Lin

Clement Hsingjen Wann

Chih-Hsin Ko

Ming-Hsi Yeh

Shih-Chi Lin

Chih-Wei Wang

Zack Chong

Kuo-Feng Yu

Yuh-Ta Fan

Cheng-Han Lee

Shih-Chieh Chang

Zheng-Yang Pan

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Inter-layer dielectrics and etch stop layers for transistor source/drain regions

Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about −2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.

Gate structure fabrication techniques for reducing gate structure warpage

Disclosed are methods for manufacturing semiconductor devices that include the operations of forming a first interconnect segment over a semiconductor substrate, forming a cap layer of a first metal over a top surface of the first interconnect segment, and modifying an exposed surface of the cap layer to form an organometallic film by adding ammonia to the top surface of the cap layer, reacting a portion of the ammonia with residual methyl radicals present on the top surface of the cap layer, and removing hydrogen from both the ammonia and the methyl radicals to form an organometallic film on the cap layer.

Semiconductor device with low-galvanic corrosion structures, and method of making same

A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Gate structure and method of forming same

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

Method of manufacturing semiconductor devices and semiconductor devices

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Method of manufacturing a semiconductor device and a semiconductor device

The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

Metal gate structures for field effect transistors

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

A method includes providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium. The method further includes forming a metal nitride layer over the high-k gate dielectric layer and performing a first treatment to the structure using a metal-containing gas. After the performing of the first treatment, the method further includes depositing a silicon layer over the metal nitride layer; and then annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer. The metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.

Semiconductor devices with metal intercalated high-k capping

A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Gate stack treatment

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.

Inner filler layer for multi-patterned metal gate for nanostructure transistor

A semiconductor structure includes a first transistor adjacent a second transistor. The first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer. The first and the second gate metal layers include different materials. The semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer. One of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum. A bottom surface of the first gate metal layer is directly on a top surface of the first barrier.

Method and structure for metal gate boundary isolation

In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.

Growing community of inventors

Hsinchu, Taiwan

Chandrashekhar Prakash Savant