Sandisk 3d LLC

Other

Sandisk Technologies Inc.

Chandrasekhar R Gorla

Roy E Scheuerlein

Pankaj Kalra

Abhijit Bandyopadhyay

Yingchang Chen

Brian Le

Xiying Costa

Masaaki Higashitani

Tz-Yi Liu

Yicheng Lu

Paul H Shen

Michael Wraback

Li Xiao

Yibo Nian

Shaohua Liang

Tao Du

Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Method of operating FET low current 3D re-ram

Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays

Method of operating FET low current 3D Re-RAM

Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Compensation scheme for non-volatile memory

Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.

Balanced method for programming multi-layer cell memories

A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.

Step soft program for reversible resistivity-switching elements

A high contrast ultrahigh speed optically-addressed ultraviolet light modulator exploits the optical anisotropy in a ZnO film epitaxially grown on sapphire. This device, which could also be realized in a ZnO bulk crystal or similar wide bandgap material, achieves both high contrast and high speed by exploiting the anisotropic bleaching of the anisotropic absorption and concomitant ultrafast polarization rotation near the lowest exciton resonances produced by femtosecond ultraviolet pulses. The resultant modulation in a preferred embodiment is characterized by a contrast ratio of 70:1, corresponding to a dynamic polarization rotation of 12&deg;, and decays to a quasi-equilibrium value within 100 ps.

High contrast, ultrafast optically-addressed ultraviolet light modulator based upon optical anisotropy

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Cupertino, CA, United States of America

Chandrasekhar R Gorla