International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Chandrasekara Kothandaraman

Dirk Pfeiffer

Anthony J Annunziata

Sami Rosenblatt

Devendra K Sadana

Ghavam G Shahidi

Chung H Lam

Vijay Narayanan

Daniel Joseph Friedman

Ramachandran Muralidhar

Eduard Albert Cartier

Frank Robert Libsch

Robert L Wisnieff

Richard Harold Boivie

Seiji Munetoh

Charanjit Singh Jutla

Kohji Hosokawa

Jeong-Heon Park

Wanki Kim

Babar Ali Khan

John Ryan Sporre

Guohan Hu

Younghyun Kim

Akil Khamisi Sutton

Kangguo Cheng

William R Tonti

John Atkinson Fifield

Chengwen Pei

Eugene John O'Sullivan

Deborah A Neumayer

Karl Robert Erickson

Phil Christopher Paone

Roger Allen Booth, Jr

Nathan P Marchack

Edward P Maciejewski

Marinus Hopstaken

George E Smith, Iii

Sundar Kumar Iyer

Junghyuk Lee

Mark E Anderson, Ii

A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.

Self-aligned and misalignment-tolerant landing pad for magnetoresistive random access memory

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a free magnetic layer formed on the tunnel barrier layer. A first boron-segregating layer is formed directly on the free magnetic layer. An anneal is performed to cause boron to leave the free magnetic layer at an interface with the first boron-segregating layer. A top electrode is formed over the memory stack.

Boron segregation in magnetic tunnel junctions

Methods and systems for generating an identifier includes testing an operational characteristic for each device in an array of pairs of devices. Each pair of devices includes a first device and a second device. The first device of each pair has a higher inter-device uniformity for the operational characteristic than the second device of the pair. The operational characteristic between the first device and the second device is compared for each pair of devices to generate a respective identifier bit for each pair of devices. An identifier is generated from the identifier bits.

Lithographically defined intrinsic identifier

Methods and systems for generating an identifier include detecting emissions from a phosphor pattern with a sensor grid comprising one or more sensors when the phosphor pattern is stimulated with radiation. An output signal of each sensor in the sensor grid is compared to a threshold value to generate respective identifier bits. An identifier is generated from the identifier bits.

Screen printed phosphors for intrinsic chip identifiers

Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices

A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.

Approach to measuring strain effects using ring oscillators

Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a fixed magnetic layer, a tunnel barrier layer on the fixed magnetic layer, and a free magnetic layer formed on the tunnel barrier layer. A boron-segregating layer is formed directly on the free magnetic layer. The memory stack is etched into a pillar. A top electrode is formed over the pillar.

Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.

Magnetic tunnel junction encapsulation using hydrogenated amorphous semiconductor material

A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Structure and method for forming programmable high-K/metal gate memory device

The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.

Non volatile memory RAD-hard (NVM-rh) system

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New York, NY, United States of America

Chandrasekara Kothandaraman