International Business Machines Corporation

Chandramouli V Kashyap

Charles Jay Alpert

Anirudh Devgan

Ying Liu

Byron Lee Krauter

David J Widiger

Haihua Su

David James Hathaway

Ruchir Puri

Alexander Joel Suess

Stephen Thomas Quay

Sharad Mehrotra

Gregory M Schaeffer

Gary S Ditlow

Soroush Abbaspour

Jiang Hu

Rama Gopal Gandham

Milos Hrkic

Kaviraj S Chopra

Chong-Nuen Chu

A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

Synthesizing current source driver model for analysis of cell characteristics

A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (C) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using Cas an effective load for said selected gate. Optionally, if the total gate load capacitance (C) exceeds Cby less than a minimum, the effective capacitance (C) is determined and used for determining the gate delay instead.

Integrated circuit (IC) chip design method, program product and system

A method for computing a Miller-factor compensated for peak noise provided. The method includes mapping at least two delays as function of at least two Miller-factors; determining an equation of the function; computing a peak noise; computing a peak delay resulting from the peak noise; and computing the compensated Miller-factor based on the equation and the peak delay. The function can be either a linear function or a non-linear function.

Methods for computing Miller-factor using coupled peak noise

A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Method for estimating propagation noise based on effective capacitance in an integrated circuit chip

A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical 'subtraction.'

Method, apparatus, and program for block-based static timing analysis with uncertainty

A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Cis computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Cis characterized by:(1&#x2212;)where Cis the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and &#x3c4;dj is the resistance of the pi-model (R) multiplied by C. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.

Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model

A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit. In another application, the invention is used to estimate output slew for the ramp input of the RC circuit. New delay and slew metrics are also disclosed which are derived by matching one or more properties of the network impulse response to a lognormal distribution. For delay, the mean and variance of a probability distribution function (PDF) are correlated to the lognormal distribution. For slew, alternative metrics are provided; one slew metric correlates the mean and variance of the PDF to the lognormal distribution, while a second slew metric correlates the variance and skewness of the PDF to the lognormal distribution.

Interconnect delay and slew metrics based on the lognormal distribution

An apparatus and method for incorporating driver sizing into buffer insertion such that the two optimization techniques are performed simultaneously are provided. The apparatus and method extends van Ginneken's algorithm to handle driver sizing by treating a source node as a 'driver library.' With the apparatus and method, the circuit design is converted to a Steiner tree representation of the circuit design. Buffer insertion is performed on the Steiner tree using the van Ginneken algorithm to generate a first set of possible optimal solutions. For each solution in the first set, a driver of the same type as the original driver in the Steiner tree is selected from a driver library and virtually inserted into the solution. A delay penalty is retrieved for the selected driver, which is then used long with the new driver's characteristics to generate a second set of solutions based o the first set of solutions.

Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique

A method of determining a circuit response (such as delay or slew) from a ramp input of an RC circuit calculates two circuit response parameters using a given circuit response metric based on a step input for the RC circuit, and extends the circuit response metric to a ramp input of the RC circuit by combining the first and second circuit response parameters to yield an estimated ramp response. The novel technique is based on the use of probability distribution functions and cumulative distribution functions to characterize the impulse response of the RC circuit, and the calculating steps derive the first and second circuit response parameters from such statistical distribution functions. In particular, the calculating steps may use a standard deviation or a mean of a probability distribution function corresponding to the circuit response parameter. In one application, the invention is used to estimate delay response for the ramp input of the RC circuit. In another application, the invention is used to estimate output slew for the ramp input of the RC circuit. The invention may be used to extend any valid delay or slew metric.

Method and system for extending delay and slew metrics to ramp inputs

Physical design optimizations for integrated circuits, such as placement, buffer insertion, floorplanning and routing, require fast and accurate analysis of resistive-capacitive (RC) delays in the network. A method is disclosed for estimating delays at nodes in an RC circuit by calculating a first and second impulse response moments of the RC circuit, and matching the impulse response moments to a Weibull distribution. Based on the match, a signal delay value is computed. The invention may thus be used to determine whether the RC circuit meets a desired optimization condition, based on the signal delay value. In the exemplary implementation, the signal delay value at a delay point is calculated by finding a percentile of the Weibull distribution corresponding to the delay point. This implementation is accurate and very efficient as it uses only two very small look-up tables.

Robust delay metric for RC circuits

A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.

Method for handling coupling effects in static timing analysis

A method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements. The method includes modeling the interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for the interconnect. In an advantageous embodiment, the realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit that includes a second resistance and first and second capacitances.

Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance

An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.

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Round Rock, TX, United States of America

Chandramouli V Kashyap